MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 141

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

11.4.5 Accuracy and Precision
11.5 Interrupts
11.6 Low-Power Modes
11.6.1 Wait Mode
11.6.2 Stop Mode
11.7 I/O Signals
MC68H(R)C908JL3
MOTOROLA
—
Rev. 1.0
The conversion process is monotonic and has no missing codes.
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit is at logic 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
The following subsections describe the ADC in low-power modes.
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting the CH[4:0] bits in the ADC Status and
Control register to logic 1’s before executing the WAIT instruction.
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
The ADC module has 12 channels that are shared with I/O port B and
port D.
Analog-to-Digital Converter (ADC)
Analog-to-Digital Converter (ADC)
Technical Data
Interrupts
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