MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 174

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

Computer Operating Properly (COP)
15.3 Functional Description
Technical Data
174
NOTE:
1. See SIM section for more details.
INTERNAL RESET SOURCES
(COPRS FROM CONFIG1)
COPD (FROM CONFIG1)
RESET VECTOR FETCH
COPEN (FROM SIM)
COPCTL WRITE
COPCTL WRITE
COP RATE SEL
2OSCOUT
RESET
Figure 15-1
The COP counter is a free-running 6-bit counter preceded by the 12-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
2
COP rate select bit, COPRS, in configuration register 1. With a 2
2OSCOUT cycle overflow option, a 8MHz crystal gives a COP timeout
period of 32.766 ms. Writing any value to location $FFFF before an
overflow occurs prevents a COP reset by clearing the COP counter and
stages 12 through 5 of the SIM counter.
18
(1)
– 2
Figure 15-1. COP Block Diagram
4
or 2
Computer Operating Properly (COP)
COP MODULE
COP CLOCK
13
shows the structure of the COP module.
12-BIT SIM COUNTER
– 2
COP COUNTER
4
6-BIT COP COUNTER
CLEAR
2OSCOUT cycles; depending on the state of the
SIM
MC68H(R)C908JL3
RESET STATUS REGISTER
SIM RESET CIRCUIT
MOTOROLA
—
18
Rev. 1.0
– 2
4