MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 186

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

Break Module (BREAK)
17.4.1 Flag Protection During Break Interrupts
17.4.2 CPU During Break Interrupts
17.4.3 TIM During Break Interrupts
17.4.4 COP During Break Interrupts
17.5 Break Module Registers
Technical Data
186
The system integration module (SIM) controls whether or not module
status bits can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state. (See
and see the Break Interrupts subsection for each module.)
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A break interrupt stops the timer counter.
The COP is disabled during a break interrupt when V
on the RST pin.
These registers control and monitor operation of the break module:
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Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
Break Module (BREAK)
7.8.3 Break Flag Control Register (BFCR)
MC68H(R)C908JL3
DD
+ V
HI
MOTOROLA
is present
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Rev. 1.0