MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 160

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

External Interrupt (IRQ)
13.4 Functional Description
Technical Data
160
A logic zero applied to the external interrupt pin can latch a CPU interrupt
request.
Interrupt signals on the IRQ1 pin are latched into the IRQ1 latch. An
interrupt latch remains set until one of the following actions occurs:
The external interrupt pin is falling-edge-triggered and is software-
configurable to be either falling-edge or falling-edge and low-level-
triggered. The MODE1 bit in the ISCR controls the triggering sensitivity
of the IRQ1 pin.
When the interrupt pin is edge-triggered only, the CPU interrupt request
remains set until a vector fetch, software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the
CPU interrupt request remains set until both of the following occur:
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic one. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE1 control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the ISCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK1 bit is clear.
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Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the IRQ latch.
Software clear — Software can clear the interrupt latch by writing
to the acknowledge bit in the interrupt status and control register
(ISCR). Writing a logic one to the ACK1 bit clears the IRQ1 latch.
Reset — A reset automatically clears the interrupt latch.
Vector fetch or software clear
Return of the interrupt pin to logic one
Figure 13-1
External Interrupt (IRQ)
shows the structure of the IRQ module.
MC68H(R)C908JL3
MOTOROLA
—
Rev. 1.0