CY7C1412KV18-333BZXI Cypress Semiconductor, CY7C1412KV18-333BZXI Datasheet - Page 10

• Manufacturer Part Number: CY7C1412KV18-333BZXI
• Description: SRAM 36MB (2Mx18) 1.8v 333MHz QDR II SRAM
• Manufacturer: Cypress Semiconductor

Specifications of CY7C1412KV18-333BZXI

• Rohs: yes
• Memory Size: 36 MB
• Organization: 2 M x 18
• Access Time: 30 ns
• Supply Voltage - Max: 1.9 V
• Supply Voltage - Min: 1.7 V
• Maximum Operating Current: 750 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-165
• Factory Pack Quantity: 136

PLL
These chips use a PLL which is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
Application Example
Figure 2
Document Number: 001-57825 Rev. *F
MASTER
ASIC)
(CPU
BUS
or
shows two QDR II used in an application.
CLKIN/CLKIN#
Delayed K#
DATA OUT
Delayed K
Source K#
Source K
DATA IN
Address
WPS#
BWS#
RPS#
Vt
R
R
R = 50ohms
D
A
R
P
S
#
Vt = Vddq/2
W
P
S
#
SRAM #1
Figure 2. Application Example
W
B
S
#
C C#
CQ/CQ#
K
ZQ
K#
Q
R = 250ohms
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in QDR I mode (with one cycle latency and a longer
access time).
CY7C1412KV18, CY7C1414KV18
D
A
R
Vt
Vt
R
P
S
#
W
P
S
#
W
B
S
#
SRAM #2
CY7C1425KV18
C C#
CQ/CQ#
K
ZQ
K#
Q
Page 10 of 33
R = 250ohms