CY7C1412KV18-333BZXI Cypress Semiconductor, CY7C1412KV18-333BZXI Datasheet - Page 8

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CY7C1412KV18-333BZXI

Manufacturer Part Number
CY7C1412KV18-333BZXI
Description
SRAM 36MB (2Mx18) 1.8v 333MHz QDR II SRAM
Manufacturer
Cypress Semiconductor
Datasheet

Specifications of CY7C1412KV18-333BZXI

Rohs
yes
Memory Size
36 MB
Organization
2 M x 18
Access Time
30 ns
Supply Voltage - Max
1.9 V
Supply Voltage - Min
1.7 V
Maximum Operating Current
750 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FBGA-165
Factory Pack Quantity
136

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1412KV18-333BZXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Pin Definitions
Document Number: 001-57825 Rev. *F
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC /72M
NC /144M
NC /288M
V
V
V
V
Pin Name
REF
DD
SS
DDQ
Power supply Power supply inputs to the core of the device.
Power supply Power supply inputs for the outputs of the device.
reference
Ground
Output
Input-
Input
Input
Input
Input
Input
Input
Input
Input
N/A
I/O
(continued)
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q
connected between ZQ and ground. Alternatively, connect this pin directly to V
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
PLL turn off  active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the operation with the PLL turned off differs from those listed in this data sheet. For normal operation,
connect this pin to a pull up through a 10 K or less pull-up resistor. The device behaves in QDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR I timing.
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Ground for the device.
[x:0]
output impedance are set to 0.2 × RQ, where RQ is a resistor
Pin Description
CY7C1412KV18, CY7C1414KV18
CY7C1425KV18
DDQ
, which enables the
Page 8 of 33

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