CY7C1412KV18-333BZXI Cypress Semiconductor, CY7C1412KV18-333BZXI Datasheet - Page 7

• Manufacturer Part Number: CY7C1412KV18-333BZXI
• Description: SRAM 36MB (2Mx18) 1.8v 333MHz QDR II SRAM
• Manufacturer: Cypress Semiconductor

Specifications of CY7C1412KV18-333BZXI

• Rohs: yes
• Memory Size: 36 MB
• Organization: 2 M x 18
• Access Time: 30 ns
• Supply Voltage - Max: 1.9 V
• Supply Voltage - Min: 1.7 V
• Maximum Operating Current: 750 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-165
• Factory Pack Quantity: 136

Pin Definitions
Document Number: 001-57825 Rev. *F
D
WPS
BWS
BWS
BWS
BWS
A
Q
RPS
C
C
K
K
CQ
CQ
Pin Name
[x:0]
[x:0]
0
1
2
3
,
,
,
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
Input clock
Input clock
Input clock
Input clock
Echo clock
Echo clock
Output-
Input-
Input-
Input-
Input-
Input-
I/O
Data input signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1425KV18  D
CY7C1412KV18  D
CY7C1414KV18  D
Write port select  active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
Byte write select 0, 1, 2, and 3  active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
CY7C1425KV18 BWS
CY7C1412KV18  BWS
CY7C1414KV18  BWS
controls D
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device.
Address inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during
active read and write operations. These address inputs are multiplexed for both read and write
operations. Internally, the device is organized as 4 M × 9 (2 arrays each of 2 M × 9) for CY7C1425KV18,
2 M × 18 (2 arrays each of 1 M × 18) for CY7C1412KV18, and 1 M × 36 (2 arrays each of 512 K × 36)
for CY7C1414KV18. Therefore, only 21 address inputs are needed to access the entire memory array
of CY7C1425KV18, 20 address inputs for CY7C1412KV18, and 19 address inputs for CY7C1414KV18.
These inputs are ignored when the appropriate port is deselected.
Data output signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q
CY7C1425KV18  Q
CY7C1412KV18  Q
CY7C1414KV18  Q
Read port select  active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tristated following the next rising edge of
the C clock. Each read access consists of a burst of two sequential transfers.
Positive input clock for output data. C is used in conjunction with C to clock out the read data from
the device. Use C and C together to deskew the flight times of various devices on the board back to the
controller. See
Negative input clock for output data. C is used in conjunction with C to clock out the read data from
the device. Use C and C together to deskew the flight times of various devices on the board back to the
controller. See
Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
Negative input clock input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in
CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the
[35:27].
Application Example on page 10
Application Example on page 10
[8:0]
[17:0]
[35:0]
[8:0]
[17:0]
[35:0]
0
0
0
controls D
controls D
[x:0]
controls D
when in single clock mode.
Switching Characteristics on page
[x:0]
Switching Characteristics on page
when in single clock mode. All accesses are initiated on the rising
[8:0].
[8:0]
[8:0]
and BWS
, BWS
Pin Description
1
for further details.
for further details.
CY7C1412KV18, CY7C1414KV18
[x:0]
1
controls D
controls D
are automatically tristated.
[17:9]
[17:9].
, BWS
25.
25.
2
controls D
CY7C1425KV18
[26:18]
Page 7 of 33
and BWS
[x:0]
3
.