CY7C1412KV18-333BZXI Cypress Semiconductor, CY7C1412KV18-333BZXI Datasheet - Page 12

• Manufacturer Part Number: CY7C1412KV18-333BZXI
• Description: SRAM 36MB (2Mx18) 1.8v 333MHz QDR II SRAM
• Manufacturer: Cypress Semiconductor

Specifications of CY7C1412KV18-333BZXI

• Rohs: yes
• Memory Size: 36 MB
• Organization: 2 M x 18
• Access Time: 30 ns
• Supply Voltage - Max: 1.9 V
• Supply Voltage - Min: 1.7 V
• Maximum Operating Current: 750 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-165
• Factory Pack Quantity: 136

Write Cycle Descriptions
The write cycle description table for CY7C1425KV18 follow.
Write Cycle Descriptions
The write cycle description table for CY7C1414KV18 follow.
Document Number: 001-57825 Rev. *F
Notes
9. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
10. Is based on a write cycle that was initiated in accordance with the
11. Is based on a write cycle that was initiated in accordance with the
BWS
BWS
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
of a write cycle, as long as the setup and hold requirements are achieved.
of a write cycle, as long as the setup and hold requirements are achieved.
0
0
L–H
L–H
BWS
K
–
–
H
H
H
H
H
H
H
H
L
L
L
L
1
L–H During the data portion of a write sequence, the single byte (D
L–H No data is written into the device during this portion of a write operation.
K
–
–
BWS
H
H
H
H
H
H
H
H
L
L
L
L
During the data portion of a write sequence, the single byte (D
No data is written into the device during this portion of a write operation.
2
BWS
H
H
H
H
H
H
H
H
L
L
L
L
3
L–H
L–H
L–H
L–H
L–H
L–H
K
–
–
–
–
–
–
L–H During the data portion of a write sequence, all four bytes (D
L–H During the data portion of a write sequence, only the lower byte (D
L–H During the data portion of a write sequence, only the byte (D
L–H During the data portion of a write sequence, only the byte (D
L–H During the data portion of a write sequence, only the byte (D
L–H No data is written into the device during this portion of a write operation.

K
–
–
–
–
–
–
represents rising edge.
During the data portion of a write sequence, all four bytes (D
the device.
the device.
During the data portion of a write sequence, only the lower byte (D
into the device. D
into the device. D
During the data portion of a write sequence, only the byte (D
device. D
device. D
During the data portion of a write sequence, only the byte (D
the device. D
the device. D
During the data portion of a write sequence, only the byte (D
the device. D
the device. D
No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
Write Cycle Descriptions
[8:0]
[8:0]
[9, 10]
[9, 11]
[17:0]
[17:0]
[26:0]
[26:0]
and D
and D
[35:9]
[35:9]
and D
and D
remains unaltered.
remains unaltered.
[35:18]
[35:18]
Comments
remains unaltered.
remains unaltered.
[35:27]
[35:27]
table. BWS
table. BWS
remains unaltered.
remains unaltered.
CY7C1412KV18, CY7C1414KV18
remains unaltered.
remains unaltered.
0
0
, BWS
, BWS
Comments
[8:0]
[8:0]
) is written into the device.
) is written into the device.
1
1
, BWS
, BWS
2
2
, and BWS
, and BWS
3
3
can be altered on different portions
can be altered on different portions
CY7C1425KV18
[17:9]
[17:9]
[35:0]
[35:0]
[26:18]
[26:18]
[35:27]
[35:27]
) is written into the
) is written into the
) are written into
) are written into
) is written into
) is written into
) is written into
) is written into
[8:0]
[8:0]
Page 12 of 33
) is written
) is written