CY7C1412KV18-333BZXI Cypress Semiconductor, CY7C1412KV18-333BZXI Datasheet - Page 25

• Manufacturer Part Number: CY7C1412KV18-333BZXI
• Description: SRAM 36MB (2Mx18) 1.8v 333MHz QDR II SRAM
• Manufacturer: Cypress Semiconductor

Specifications of CY7C1412KV18-333BZXI

• Rohs: yes
• Memory Size: 36 MB
• Organization: 2 M x 18
• Access Time: 30 ns
• Supply Voltage - Max: 1.9 V
• Supply Voltage - Min: 1.7 V
• Maximum Operating Current: 750 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-165
• Factory Pack Quantity: 136

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-57825 Rev. *F
t
t
t
t
t
t
Setup Times
t
t
t
t
Hold Times
t
t
t
t
Parameter
29. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250
30. When a part with a maximum frequency above 250 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is
31. This part has a voltage regulator internally; t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
Cypress
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I
operated and outputs data with the output timings of that frequency range.
Parameters
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
Parameter
[29, 30]
V
K clock and C clock cycle time
Input clock (K/K; C/C) HIGH
Input clock (K/K; C/C) LOW
K clock rise to K clock rise and C
to C rise (rising edge to rising
edge)
K/K clock rise to C/C clock rise
(rising edge to rising edge)
Address set-up to K clock rise
Control set-up to K clock rise
(RPS, WPS)
DDR control set-up to clock (K/K)
rise (BWS
D
Address hold after K clock rise
Control hold after K clock rise
(RPS, WPS)
DDR control hold after clock (K/K)
rise (BWS
D
DD
[X:0]
[X:0]
(typical) to the first access
hold after clock (K/K) rise
set-up to clock (K/K) rise
0
0
Description
, BWS
, BWS
POWER
is the time that the power must be supplied above V
1
1
, BWS
, BWS
2
2
, BWS
, BWS
OL
[31]
/I
3
3
OH
)
)
and load capacitance shown in (a) of
1.20
1.20
1.35
Min
0.3
0.3
0.3
0.3
3.0
0.3
0.3
0.3
0.3
1
0
333 MHz
Max
1.30
8.4
–
–
–
–
–
–
–
–
–
–
–
–
CY7C1412KV18, CY7C1414KV18
DD(minimum)
1.32
1.32
1.49
Min
3.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
1
0
300 MHz
Figure 5 on page
initially before initiating a read or write operation.
Max
1.45
8.4
–
–
–
–
–
–
–
–
–
–
–
–
24.
CY7C1425KV18
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
Min
4.0
1.6
1.6
1.8
1
0
250 MHz

, V
DDQ
Max
Page 25 of 33
8.4
1.8
–
–
–
–
–
–
–
–
–
–
–
–
= 1.5 V, input
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns