CY7C1412KV18-333BZXI Cypress Semiconductor, CY7C1412KV18-333BZXI Datasheet - Page 11

• Manufacturer Part Number: CY7C1412KV18-333BZXI
• Description: SRAM 36MB (2Mx18) 1.8v 333MHz QDR II SRAM
• Manufacturer: Cypress Semiconductor

Specifications of CY7C1412KV18-333BZXI

• Rohs: yes
• Memory Size: 36 MB
• Organization: 2 M x 18
• Access Time: 30 ns
• Supply Voltage - Max: 1.9 V
• Supply Voltage - Min: 1.7 V
• Maximum Operating Current: 750 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-165
• Factory Pack Quantity: 136

Truth Table
The truth table for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow.
Write Cycle Descriptions
The write cycle description table for CY7C1412KV18 follow.
Document Number: 001-57825 Rev. *F
Notes
Write cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
Read cycle:
Load address on the rising edge of K;
wait one and a half cycle; read data on C and C rising edges.
NOP: No operation
Standby: Clock stopped
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
8. Is based on a write cycle that was initiated in accordance with the
BWS
H
H
H
H
L
L
L
L
symmetrically.
of a write cycle, as long as the setup and hold requirements are achieved.
0
BWS
H
H
H
H
L
L
L
L
1
L–H
L–H
L–H
L–H
K
–
–
–
–
L–H During the data portion of a write sequence:
L–H During the data portion of a write sequence
L–H During the data portion of a write sequence
L–H No data is written into the devices during this portion of a write operation.
Operation
K
–
–
–
–
During the data portion of a write sequence
CY7C1412KV18 both bytes (D
CY7C1412KV18 both bytes (D
During the data portion of a write sequence:
CY7C1412KV18 only the lower byte (D
CY7C1412KV18 only the lower byte (D
During the data portion of a write sequence
CY7C1412KV18 only the upper byte (D
CY7C1412KV18 only the upper byte (D
No data is written into the devices during this portion of a write operation.

represents rising edge.
Write Cycle Descriptions
[2, 8]
Stopped
[17:0]
[17:0]
L–H
L–H
L–H
K
) are written into the device.
) are written into the device.
[8:0]
[8:0]
[17:9]
[17:9]
RPS WPS
table. BWS
Comments
) is written into the device, D
) is written into the device, D
X
H
X
L
) is written into the device, D
) is written into the device, D
CY7C1412KV18, CY7C1414KV18
H
X
X
L
[2, 3, 4, 5, 6, 7]
0
, BWS
D(A + 0) at K(t) 
Q(A + 0) at C(t + 1)  Q(A + 1) at C(t + 2) 
D = X
Q = high Z
Previous state
1
, BWS
2
, and BWS
DQ
[17:9]
[17:9]
3
can be altered on different portions
[8:0]
[8:0]
CY7C1425KV18
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
D(A + 1) at K(t) 
D = X
Q = high Z
Previous state
Page 11 of 33
DQ