CY7C1412KV18-333BZXI Cypress Semiconductor, CY7C1412KV18-333BZXI Datasheet - Page 26

• Manufacturer Part Number: CY7C1412KV18-333BZXI
• Description: SRAM 36MB (2Mx18) 1.8v 333MHz QDR II SRAM
• Manufacturer: Cypress Semiconductor

Specifications of CY7C1412KV18-333BZXI

• Rohs: yes
• Memory Size: 36 MB
• Organization: 2 M x 18
• Access Time: 30 ns
• Supply Voltage - Max: 1.9 V
• Supply Voltage - Min: 1.7 V
• Maximum Operating Current: 750 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-165
• Factory Pack Quantity: 136

Switching Characteristics
Over the Operating Range
Document Number: 001-57825 Rev. *F
Output Times
t
t
t
t
t
t
t
t
t
t
PLL Timing
t
t
t
Notes
Parameter
CO
DOH
CCQO
CQOH
CQD
CQDOH
CQH
CQHCQH
CHZ
CLZ
KC Var
KC lock
KC Reset
32. These parameters are extrapolated from the input timing parameters (t
33. t
34. At any voltage and temperature t
35. For frequencies 300 MHz or below, the Cypress QDR II devices surpass the QDR consortium specification for PLL lock time (tKC lock) of 20 µs (min. spec.) and will
Cypress
Parameters
design and are not tested in production.
lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version.
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
CHQZ
CHQX1
KC Var
KC lock
KC Reset
Parameter
[29, 30]
C/C clock rise (or K/K in single
clock mode) to data valid
Data output hold after output C/C
clock rise (active to active)
C/C clock rise to echo clock valid
Echo clock hold after C/C clock
rise
Echo clock high to data valid
Echo clock high to data invalid
Output clock (CQ/CQ) HIGH
CQ clock rise to CQ clock rise
(rising edge to rising edge)
Clock (C/C) rise to high Z (active
to high Z)
Clock (C/C) rise to low Z
Clock phase jitter
PLL lock time (K, C)
K static to PLL reset
CHZ
is less than t
[33, 34]
Description
(continued)
CLZ
and t
[35]
CHZ
[33, 34]
less than t
[32]
[32]
CYC
Figure 5 on page
CO
/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
–0.45
–0.45
–0.25
–0.45
.
1.25
1.25
Min
20
30
–
–
–
–
333 MHz
24. Transition is measured  100 mV from steady state voltage.
0.45
0.25
0.20
Max
0.45
0.45
–
–
–
–
–
–
–
–
CY7C1412KV18, CY7C1414KV18
–0.45
–0.45
–0.27
–0.45
1.40
1.40
Min
20
30
–
–
–
–
300 MHz
Max
0.45
0.45
0.27
0.45
0.20
–
–
–
–
–
–
–
–
CY7C1425KV18
–0.45
–0.45
–0.30
–0.45
1.75
1.75
Min
20
30
–
–
–
–
–
250 MHz
Max
0.45
0.45
0.30
0.45
0.20
Page 26 of 33
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ns