C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 166

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

C8051F020/1/2/3
17.1.7. External Memory Interface Pin Assignments
If the External Memory Interface (EMIF) is enabled on the Low ports (Ports 0 through 3), EMIFLE (XBR2.1) should
be set to a logic 1 so that the Crossbar will not assign peripherals to P0.7 (/WR), P0.6 (/RD), and if the External Mem-
ory Interface is in Multiplexed mode, P0.5 (ALE). Figure 17.4 shows an example Crossbar Decode Table with
EMIFLE=1 and the EMIF in Multiplexed mode. Figure 17.5 shows an example Crossbar Decode Table with
EMIFLE=1 and the EMIF in Non-multiplexed mode.
If the External Memory Interface is enabled on the Low ports and an off-chip MOVX operation occurs, the External
Memory Interface will control the output states of the affected Port pins during the execution phase of the MOVX
instruction, regardless of the settings of the Crossbar registers or the Port Data registers. The output configuration of
the Port pins is not affected by the EMIF operation, except that Read operations will explicitly disable the output
drivers on the Data Bus. See
XRAM” on page 145
166
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
TX1
RX1
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
CP0
CP1
T0
/INT0
T1
/INT1
T2
T2EX
T4
T4EX
/SYSCLK
CNVSTR
PIN I/O 0
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2
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3
P0
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EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xFF)
4
5
for more information about the External Memory Interface.
6
7
Figure 17.4. Priority Crossbar Decode Table
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0
AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L
Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP
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1
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2
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3
P1
4
5
6
7
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0
Rev. 1.4
1
2
3
P2
4
5
6
7
0
Muxed Data/Non-muxed Data
1
2
3
P3
4
5
6
7
Crossbar Register Bits
UART0EN:
UART1EN:
SMB0EN:
PCA0ME:
SYSCKE: XBR1.7
CNVSTE: XBR2.0
SPI0EN:
T2EXE: XBR1.6
T4EXE: XBR2.4
ECI0E: XBR0.6
INT0E: XBR1.2
INT1E: XBR1.4
CP0E: XBR0.7
CP1E: XBR1.0
T0E: XBR1.1
T1E: XBR1.3
T2E: XBR1.5
T4E: XBR2.3
XBR0.2
XBR0.1
XBR0.0
XBR2.2
XBR0.[5:3]