C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 29

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

1.8.
The C8051F020/1/2/3 has an on-board 8-bit SAR ADC (ADC1) with an 8-channel input multiplexer and programma-
ble gain amplifier. This ADC features a 500 ksps maximum throughput and true 8-bit accuracy with an INL of
±1LSB. Eight input pins are available for measurement. The ADC is under full control of the CIP-51 microcontroller
via the Special Function Registers. The ADC1 voltage reference is selected between the analog power supply (AV+)
and an external VREF pin. On C8051F020/2 devices, ADC1 has its own dedicated VREF1 input pin; on
C8051F021/3 devices, ADC1 shares the VREFA input pin with the 12/10-bit ADC0. User software may put ADC1
into shutdown mode to save power.
A programmable gain amplifier follows the analog multiplexer. The gain stage can be especially useful when differ-
ent ADC input channels have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal
with a large DC offset (in differential mode, a DAC could be used to provide the DC offset). The PGA gain can be set
in software to 0.5, 1, 2, or 4.
A flexible conversion scheduling system allows ADC1 conversions to be initiated by software commands, timer
overflows, or an external input signal. ADC1 conversions may also be synchronized with ADC0 software-com-
manded conversions. Conversion completions are indicated by a status bit and an interrupt (if enabled), and the
resulting 8-bit data word is latched into an SFR upon completion.
8-Bit Analog to Digital Converter
AIN1.0
AIN1.1
AIN1.2
AIN1.3
AIN1.4
AIN1.5
AIN1.6
AIN1.7
Analog Multiplexer
AMUX
8-to-1
Figure 1.12. 8-Bit ADC Diagram
Programmable Gain
X
Amplifier
External VREF
Configuration, Control, and Data Registers
+
-
AV+
AV+
Pin
Rev. 1.4
ADC
VREF
8-Bit
SAR
Start Conversion
8
C8051F020/1/2/3
ADC Data
Register
Write to AD1BUSY
Timer 3 Overflow
CNVSTR Input
Timer 2 Overflow
Write to AD0BUSY
(synchronized with
ADC0)
Conversion
Complete
Interrupt
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