C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 260
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
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C8051F020/1/2/3
260
Bit7:
Bits6-4:
Bits3-1:
Bit0:
CIDL
R/W
Bit7
CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
UNUSED. Read = 000b, Write = don't care.
CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
These bits select the timebase source for the PCA0 counter
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
†
‡
The minimum high or low time for the ECI input signal is at least 2 system clock cycles.
External oscillator source divided by 8 is synchronized with the system clock.
CPS2
0
0
0
0
1
1
1
1
R/W
Bit6
CPS1
Figure 23.11. PCA0MD: PCA0 Mode Register
0
0
1
1
0
0
1
1
R/W
Bit5
CPS0
0
1
0
1
0
1
0
1
R/W
Bit4
-
Timebase
Rev. 1.4
CPS2
R/W
Bit3
(max rate = system clock divided by 4)
High-to-low transitions on ECI
External clock divided by 8
System clock divided by 12
System clock divided by 4
CPS1
R/W
Bit2
Timer 0 overflow
System clock
Reserved
Reserved
CPS0
R/W
Bit1
‡
ECF
R/W
Bit0
†
SFR Address:
01000000
Reset Value
0xD9
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