DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet
DF2170BVTE33V
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DF2170BVTE33V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2172 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series The revision list can be viewed directly by cliking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by ...
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Rev. 2.00, 03/04, page ii of xxxii ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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This LSI is a microcomputer (MCU) made up of the H8S/2000 CPU employing Renesas Technolgy's original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general ...
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Examples: Register name: Bit order: Number notation: Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. (http://www.renesas.com/eng/) TM H8S/2170 F-ZTAT ...
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Rev. 2.00, 03/04, page viii of xxxii ...
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Section 1 Overview............................................................................................1 1.1 Features............................................................................................................................. 1 1.2 Internal Block Diagram..................................................................................................... 2 1.3 Pin Description.................................................................................................................. 3 1.3.1 Pin Arrangement .................................................................................................. 3 1.3.2 Pin Arrangements in Each Mode ......................................................................... 4 1.3.3 Pin Functions ....................................................................................................... 8 Section 2 CPU....................................................................................................13 2.1 Features............................................................................................................................. 13 2.1.1 ...
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Effective Address Calculation ............................................................................. 44 2.8 Processing States............................................................................................................... 46 2.9 Usage Note........................................................................................................................ 47 2.9.1 Note on Bit Manipulation Instructions ................................................................ 47 Section 3 MCU Operating Modes ..................................................................... 49 3.1 Operating Mode Selection ................................................................................................ 49 3.2 Register Descriptions........................................................................................................ 50 3.2.1 ...
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Interrupt Control Mode 1 ..................................................................................... 76 5.6.3 Interrupt Exception Handling Sequence .............................................................. 78 5.6.4 Interrupt Response Times .................................................................................... 80 5.7 Usage Notes ...................................................................................................................... 81 5.7.1 Conflict between Interrupt Generation and Disabling ......................................... 81 5.7.2 Instructions that Disable Interrupts ...................................................................... ...
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Precharge State Control ....................................................................................... 128 6.6.9 Wait Control ........................................................................................................ 129 6.6.10 Byte Access Control ............................................................................................ 131 6.6.11 Burst Operation.................................................................................................... 132 6.6.12 Refresh Control.................................................................................................... 137 6.6.13 DMAC Single Address Transfer Mode and DRAM Interface............................. 140 6.7 Idle Cycle.......................................................................................................................... 142 6.7.1 ...
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Section 8 I/O Ports .............................................................................................219 8.1 Port 1................................................................................................................................. 222 8.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 222 8.1.2 Port 1 Data Register (P1DR)................................................................................ 223 8.1.3 Port 1 Register (PORT1)...................................................................................... 223 8.1.4 Pin Functions ....................................................................................................... 224 8.2 Port 2................................................................................................................................. 226 8.2.1 ...
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Port 9 Data Register (P9DR) ............................................................................... 255 8.9.3 Port 9 Register (PORT9)...................................................................................... 255 8.9.4 Pin Functions ....................................................................................................... 256 8.10 Port A................................................................................................................................ 258 8.10.1 Port A Data Direction Register (PADDR)........................................................... 258 8.10.2 Port A Data Register (PADR).............................................................................. 258 8.10.3 Port ...
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Section 10 Watchdog Timer (WDT)..................................................................283 10.1 Features............................................................................................................................. 283 10.2 Register Descriptions ........................................................................................................ 284 10.2.1 Timer Counter (TCNT)........................................................................................ 284 10.2.2 Timer Control/Status Register (TCSR)................................................................ 284 10.3 Operation .......................................................................................................................... 286 10.3.1 Watchdog Timer Mode ........................................................................................ 286 10.3.2 Interval Timer Mode............................................................................................ 287 10.3.3 ...
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Section 12 Universal Serial Bus 2 (USB2)........................................................ 319 12.1 Features............................................................................................................................. 319 12.2 Input/Output Signals ......................................................................................................... 321 12.3 Register Descriptions........................................................................................................ 322 12.3.1 Interrupt Flag Register 0 (IFR0) .......................................................................... 323 12.3.2 Interrupt Select Register 0 (ISR0)........................................................................ 328 12.3.3 Interrupt Enable Register 0 ...
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Usage Notes ...................................................................................................................... 364 12.8.1 Setup Data Reception........................................................................................... 364 12.8.2 FIFO Clear ........................................................................................................... 364 12.8.3 Operating Frequency............................................................................................ 364 12.8.4 Interrupts.............................................................................................................. 364 12.8.5 Register Access Size ............................................................................................ 364 12.8.6 Data Register Overread or Overwrite .................................................................. 365 12.8.7 EP0 Interrupt Sources ...
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Flash Memory Emulation in RAM ................................................................................... 432 14.7.1 Emulation in RAM .............................................................................................. 432 14.7.2 RAM Overlap ...................................................................................................... 433 14.8 Programmer Mode ............................................................................................................ 434 14.9 Serial Communication Interface Specification for Boot Mode......................................... 435 14.10 Usage Notes ...................................................................................................................... 461 Section 15 ...
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Bus Timing .......................................................................................................... 504 18.3.4 DMAC Timing..................................................................................................... 515 18.3.5 Timing of On-Chip Peripheral Modules .............................................................. 518 18.4 Flash Memory Characteristics .......................................................................................... 521 18.4.1 Flash Memory Characteristics ............................................................................. 521 18.5 Use Note (Internal Voltage Step Down) ........................................................................... 522 Appendix .........................................................................................................523 ...
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Rev. 2.00, 03/04, page xx of xxxii ...
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Section 1 Overview Figure 1.1 Internal Block Diagram ................................................................................................. 2 Figure 1.2 Pin Arrangement (TFP-100B) ....................................................................................... 3 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 17 Figure 2.2 Stack Structure in Normal Mode ................................................................................. 17 Figure 2.3 Exception ...
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Figure 6.3 Read Strobe Negation Timing (Example of 3-State Access Space) ............................ 93 Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access)................................................. 97 Figure 6.5 Area Divisions........................................................................................................... 102 Figure 6.6 Address Format ......................................................................................................... 103 Figure 6.7 ...
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Figure 6.41 Example of Timing when Precharge Time after Self-Refreshing is Extended by 2 States................................................................................................................ 140 Figure 6.42 Example of DACK Output Timing when DDS = 1 (RAST = 0, CAST = 0) .......... 141 Figure 6.43 Example of DACK ...
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Figure 7.25 Example of Single Address Mode (Word Read) Transfer....................................... 196 Figure 7.26 Example of Single Address Mode (Longword Read) Transfer ............................... 197 Figure 7.27 Example of Single Address Mode (Byte Write) Transfer ....................................... 197 Figure 7.28 Example of Single ...
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Section 9 8-Bit Timer (TMR) Figure 9.1 Block Diagram of 8-Bit Timer Module..................................................................... 264 Figure 9.2 Example of Pulse Output........................................................................................... 270 Figure 9.3 Count Timing for Internal Clock Input...................................................................... 271 Figure 9.4 Count Timing for External Clock Input .................................................................... 271 ...
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Figure 12.5 Setup Stage Operation ............................................................................................. 344 Figure 12.6 Data Stage Operation (Control-In) .......................................................................... 345 Figure 12.7 Data Stage Operation (Control-Out) ....................................................................... 346 Figure 12.8 Status Stage Operation (Control-In)........................................................................ 347 Figure 12.9 Status Stage Operation (Control-Out) ..................................................................... 348 Figure 12.10 ...
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Figure 14.26 Erasure Sequence .................................................................................................. 454 Section 15 Clock Pulse Generator Figure 15.1 Block Diagram of Clock Pulse Generator ............................................................... 463 Figure 15.2 Connection of Crystal Resonator (Example)........................................................... 464 Figure 15.3 Crystal Resonator Equivalent Circuit ...................................................................... 464 Figure 15.4 External ...
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Figure 18.28 USB2 Input/output Timing.................................................................................... 520 Figure 18.29 VCL Capacitor Connection Method...................................................................... 522 Appendix Figure C.1 Package Dimensions (TFP-100B) ............................................................................ 526 Rev. 2.00, 03/04, page xxviii of xxxii ...
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Section 1 Overview Table 1.1 Pin Arrangements in Each Mode............................................................................. 4 Table 1.2 Pin Functions........................................................................................................... 8 Section 2 CPU Table 2.1 Instruction Classification....................................................................................... 29 Table 2.2 Operation Notation ................................................................................................ 30 Table 2.3 Data Transfer Instructions ..................................................................................... 31 Table 2.4 Arithmetic ...
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Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration .................................................................................................. 85 Table 6.2 Address Map ....................................................................................................... 104 Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ..................................... 106 Table 6.4 Data Buses Used and Valid Strobes .................................................................... 110 Table ...
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Section 14 Flash Memory (0.18-µm F-ZTAT Version) Table 14.1 Comparison of Programming Modes .................................................................. 376 Table 14.2 Pin Configuration ................................................................................................ 381 Table 14.3 Register/Parameter and Target Mode .................................................................. 382 Table 14.4 Flash Memory Area Divisions............................................................................. 391 Table 14.5 Parameters and ...
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Features • High-speed H8S/2000 CPU with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions • Various peripheral functions DMA controller (DMAC) ...
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Internal Block Diagram Figure 1.1 shows the internal block diagram. MD1 FWE EXTAL XTAL NMI HUDITCK RxD0/HUDITDI TxD0/HUDITDO HUDIMS PA3/A19/ PA2/A18/ PA1/A17 PA0/A16/( ) P97/φ P96/ P95/ P94/ P93/ P92/ / P91/ P90/ P87/D15 P86/D14 P85/D13 P84/D12 ...
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Pin Description 1.3.1 Pin Arrangement Figure 1.2 shows the pin arrangement. P72/A2/ 76 P71/A1/ 77 P70/A0/ 78 P87/D15 79 P86/D14 80 P85/D13 81 P84/D12 82 P83/D11 83 P82/D10 84 P81/D9 85 P80/D8 86 VCC 87 FWE 88 89 VSS ...
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Pin Arrangements in Each Mode Table 1.1 lists the pin arrangements in each mode. Table 1.1 Pin Arrangements in Each Mode Pin No. Pin Name TFP- Extended Mode 100B (EXPE = 1) 1 PA2/A18/UCAS 2 PA3/A19/CS3 MD2 3 4 ...
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Pin No. Pin Name TFP- Extended Mode 100B (EXPE = 1) 28 P35/(IRQ5)/USVBUS 29 P36/USOPM0 30 P37/USOPM1 31 P20/USD0/DREQ0 32 P21/USD1/TEND0 33 P22/USD2/DACK0 34 P23/USD3/DRAK0 35 P24/USD4/DREQ1 36 P25/USD5/TEND1 37 P26/USD6/DACK1 38 P27/USD7/DRAK1 39 HUDITDI/RxD0 40 VSS 41 HUDITCK 42 ...
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Pin No. Pin Name TFP- Extended Mode 100B (EXPE = 1) 60 P66/A14/TMO1 61 P65/A13/TMRI1 62 P64/A12/TMCI1 63 P63/A11 64 P62/A10/TMO0 65 P61/A9/TMRI0 66 P60/A8/TMCI0 67 HUDITMS 68 VCC 69 HUDITDO/TxD0 70 VSS 71 P77/A7/IRQ7 72 P76/A6/IRQ6 73 P75/A5/IRQ5 74 ...
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Pin No. Pin Name TFP- Extended Mode 100B (EXPE = 1) 92 P56/D6/(IRQ6)/DACK3 93 P55/D5/MSBS/TEND3 94 P54/D4/MSDIO3/DREQ3 95 P53/D3/(IRQ3)/MSDIO2/DRAK2 P53/(IRQ3)/MSDIO2/DRAK2 96 P52/D2/(IRQ2)/MSDIO1/DACK2 P52/(IRQ2)/MSDIO1/DACK2 97 P51/D1/MSDIO0/TEND2 98 P50/D0/MSCLK/DREQ2 99 PA0/A16/(IRQ0) 100 PA1/A17/LCAS/(IRQ1) Single-Chip Mode (EXPE = 0) P56/(IRQ6)/DACK3 P55/MSBS/TEND3 P54/MSDIO3/DREQ3 P51/MSDIO0/TEND2 ...
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Pin Functions Table 1.2 lists the pin functions. Table 1.2 Pin Functions Type Symbol Pin No. Power V 14, 42 11, 40 Clock XTAL 13 EXTAL 12 φ ...
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Type Symbol Pin No. Interrupt NMI 6 signals IRQ7 IRQ0 (IRQ7) to 91, 92, (IRQ0) 28, 27, 95, 96, 99, 100 Address bus A19 2, A18 1, A17 100, A16 99, A15 ...
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Type Symbol Pin No. DREQ3 DMA 94, DREQ2 controller 98, DREQ1 (DMAC) 35, DREQ0 31 DACK3 92 DACK2 96 DACK1 37 DACK0 33 TEND3 93, TEND2 97, TEND1 36, TEND0 32 DRAK3 91, DRAK2 95, DRAK1 38, DRAK0 34 8-bit ...
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Type Symbol Pin No. USRST Universal 51 serial bus 2 USTXV 27 (USB2) USSUSP 55 USTSEL 56 USXCVRS 58 USD15 43, USD8 USD7 to USD0 I/O ports P17 to P10 P27 ...
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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Two CPU operating modes Normal mode* Advanced mode Note: For this LSI, normal mode is not available. • Power-down state Transition to power-down state by SLEEP instruction 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. ...
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CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 ...
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H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 H'0007 H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode (16 bits) ...
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Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as ...
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The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a ...
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Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The ...
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Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and ...
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General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...
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Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by ...
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Initial Bit Bit Name Value 0 C Undefined R/W 2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask ...
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Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En [Legend] ERn : General register General register General register R RnH : General register RH RnL ...
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Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made ...
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Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* LDM, STM MOVFPE* Arithmetic ADD, ...
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Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description Rd General register (destination)* Rs ...
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Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot ...
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Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data and data in a ...
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Table 2.4 Arithmetic Operations Instructions (2) 1 Instruction Size* Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 ...
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Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → ...
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Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...
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Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the ...
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Table 2.8 Branch Instructions Instruction Size Function Bcc Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC ...
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Table 2.9 System Control Instructions Instruction Size* Function TRAPA Starts trap-instruction exception handling. RTE Returns from an exception-handling routine. SLEEP Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR LDC B/W Moves the ...
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Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B else next: ≠ 0 then EEPMOV.W else next: Transfers a data block. Starting from the address set in ER5, transfers data ...
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Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and ...
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Register DirectRn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers and E0 ...
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A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 ...
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In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed (H'00). Note ...
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Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address ...
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Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Note: For this LSI, normal mode is not available. Effective Address Calculation PC contents Sign extension Memory contents Memory contents Rev. 2.00, 03/04, page 45 of ...
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Processing States The H8S/2000 CPU has four main processing states: the reset state, exception handling state, program execution state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and internal ...
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Exception handling state = High *1 Reset state Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever A transition can also be made to the reset state when the watchdog ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports single operating mode (mode 2). The operating mode is determined by the setting of the mode pins (MD2 and MD1). Table 3.1 shows the MCU operating mode selection. ...
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Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current ...
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System Control Register (SYSCR) SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for NMI, and controls on-chip RAM address space. Initial Bit Bit Name Value All 0 5 INTM1 0 ...
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Operating Modes 3.3.1 Mode 2 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE ...
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Address Map Figure 3.1 shows the address map in each operating mode. ROM: 256 kbytes RAM: 32 kbytes Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM H'000000 H'040000 H'FF7000 H'FFF000 H'FFFC00 H'FFFF00 H'FFFF40 H'FFFFFF Note: ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions ...
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Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.2 Exception Handling Vector Table Exception Source Reset Reserved for system use External ...
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Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ...
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RES Internal address bus Internal read signal Internal write signal Internal data bus (1), (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2), (4) Start address (contents of reset exception handling vector address) (5) Start ...
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Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI and IRQ7 to IRQ0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt ...
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Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Figure 4.2 Stack Status after Exception Handling 4.7 Usage Note When accessing word data or longword data, this ...
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SP SP TRAPA instruction executed SP set to H'FFFEFF Legend CCR : Condition code register PC : Program counter R1L : General register R1L SP : Stack pointer Note: This diagram illustrates an example in which the interrupt control mode ...
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Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An ...
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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Symbol I/O NMI Input IRQ7 to IRQ0 Input 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control ...
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Table 5.2 Correspondence between Interrupt Source and ICR Bit Bit Name ICRA 7 ICRn7 IRQ0 6 ICRn6 IRQ1 5 ICRn5 IRQ2, IRQ3 4 ICRn4 IRQ4, IRQ5 3 ICRn3 IRQ6, IRQ7 2 ICRn2 — 1 ICRn1 WDT 0 ICRn0 Refresh timer ...
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Break Address Registers (PBARA to PBARC) The PBAR registers specify an address that break address. An address in which the first byte of an instruction exists should be set as a break ...
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IRQ Sense Control Registers H, L (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0. The IRQ7 to IRQ0 pins can be switched to input pins by setting the IRQ ...
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IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0. Initial Bit Bit Name Value 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 ...
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Interrupt Sources 5.4.1 External Interrupts There are two external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted ...
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Internal Interrupts Internal interrupts issued from the on-chip peripheral modules have the following features: • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of ...
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Origin of Interrupt Source Name External pin SUSRI (Suspend recover interrupt) Reserved for system use DMAC DEND0 DEND1 DEND2 DEND3 Reserved for system use TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match B) OVI0 (Overflow) Reserved for system ...
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Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted ...
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Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.5 shows the ...
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Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests other than NMI and address break are masked by ICR and the I bit of the CCR in the CPU. The interrupt requests are held pending when the ...
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An interrupt with interrupt control level 1? IRQ0 Yes Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Program execution state Interrupt generated? Yes Yes NMI No No Yes No IRQ0 No Yes IRQ1 Yes ...
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Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR ...
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Figure 5.6 shows a flowchart of the interrupt acceptance operation interrupt source occurs when the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. 2. According to the interrupt ...
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An interrupt with interrupt control level 1? IRQ0 Yes Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case ...
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Figure 5.7 Interrupt Exception Handling Rev. 2.00, 03/04, page 79 of 534 ...
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Interrupt Response Times Table 5.7 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.7 are explained ...
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Usage Notes 5.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to ...
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Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit ...
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Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into four areas. The bus specifications such as the bus width and number of access states can be set independently ...
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Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DMAC • Others A refresh counter (refresh timer) can be used as an interval timer Internal address bus Internal bus control signals CPU bus ...
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Input/Output Pins Table 6.1 shows the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Address strobe Read High write Low write Chip select 0 Chip select 1 Chip select 2/ row address strobe Chip select 3 ...
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Register Descriptions The bus controller has the following registers. • Access control register (ACSCR) • CS assertion period control register (CSACR) • Wait control register (WTCR) • Bus control register (BCR) • Read strobe timing control register (RDNCR) • ...
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Access Control Register (ACSCR) ACSCR designates each area in the external address space as either 8-bit access space or 16-bit access space. ACSCR designates each area in the external address space as either 2-state access space or 3-state access ...
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CS Assertion Period Control Register (CSACR) 6.3.2 CSACR selects whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals extended. Extending the assertion period of the CSn and address ...
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Address Read (when RDNn = 0) Data bus , Write Data bus Note Figure 6.2 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) Bus cycle ...
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Wait Control Register (WTCR) WTCR selects the number of program wait states for each area in the external address space. Initial Bit Bit Name Value W32 1 13 W31 1 12 W30 1 11 ...
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Initial Bit Bit Name Value 6 W12 1 5 W11 1 4 W10 1 W02 1 1 W01 1 0 W00 1 R/W Description R/W Area 1 Wait Control R/W These bits select ...
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Bus Control Register (BCR) BCR is used for idle cycle settings and enabling or disabling of the write data buffer function. Initial Bit Bit Name Value All 0 8 WDBE 0 ...
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Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a read access to normal space. Initial Bit Bit Name Value 7 RDN3 0 6 RDN2 0 5 RDN1 0 4 RDN0 0 ...
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DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM interface settings. Initial Bit Bit Name Value RAST 0 CAST 0 All 0 8 DSET 0 7 ...
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Initial Bit Bit Name Value 6 RCDM 0 5 DDS 0 All 0 R/W Description RAS Down Mode R/W When access to DRAM space is interrupted by an access to normal space, an access to an internal ...
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Initial Bit Bit Name Value 2 MXC2 0 1 MXC1 0 0 MXC0 0 Rev. 2.00, 03/04, page 96 of 534 R/W Description R/W Address Multiplex Select R/W These bits select the size of the shift toward the lower half ...
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Address RAST = 0 RAS RAST = 1 RAS UCAS, LCAS Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access) 6.3.7 DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM interface bus specifications. ...
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Initial Bit Bit Name Value 1 RCD1 0 0 RCD0 0 6.3.8 Refresh Control Register (REFCR) REFCR specifies DRAM interface refresh control. Initial Bit Bit Name Value 15 CMF 0 14 CMIE 0 Rev. 2.00, 03/04, page 98 of 534 ...
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Initial Bit Bit Name Value 13 RCW1 0 12 RCW0 0 RTCK2 0 9 RTCK1 0 8 RTCK0 0 7 RFSHE 0 R/W Description CAS-RAS Wait Control R/W R/W These bits select the ...
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Initial Bit Bit Name Value 5 RLW1 0 4 RLW0 0 3 SLFRF 0 2 TPCS2 0 1 TPCS1 0 0 TPCS0 0 Note: Only 0 can be written, to clear the flag. Rev. 2.00, 03/04, page 100 of 534 ...
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Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to ...
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Bus Control 6.4.1 Area Division The bus controller divides the 16-Mbyte address space into areas shown in figure 6.5, and performs bus control for external address space in area units. Chip select signals (CS0 to CS3) can be output ...
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Address Map Figure 6.6 shows the address format. A31 to A24 A23 to A21 Don't care Do not affect the operation. A20 Reserved Does not output a signal. CS space Decoded and output CS0 to CS3 signals. A23 A22 ...
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Bits A31 to A24 do not affect the operation. Bits A23 to A21 are decoded by the chip select signals (CS3 to CS0) for each area and output. Bit A20 is not output externally. Bits A19 to A0 are output ...
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Bus Specifications The external address space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (CS) assertion period extension states. The bus width and number ...
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Number of Access States: Two or three access states can be selected with ACSCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a ...
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Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in the basic ...
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Area 3: Area 3 includes the on-chip RAM and internal I/O registers. The space excluding the on- chip RAM and internal I/O registers is external address space by setting the EXPE bit in MDCR to 1. The on-chip RAM is ...
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Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus ...
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Byte size • Even address Byte size • Odd address Word size 1st bus cycle Longword size 2nd bus cycle Figure 6.10 Access Sizes and Data Alignment Control (16-bit Access Space) 6.5.2 Valid Strobes Table 6.4 shows the data buses ...
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When all areas are designated as 8-bit space, the LWR pin can be used as the I/O port. However, when all areas are designated as 16-bit space, the LWR pin is always fixed high. Wait states cannot be inserted. φ ...
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Access Space: Figure 6.12 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. When all areas are designated ...
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Access Space: Figures 6.13 to 6.15 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and ...
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Address bus D15 to D8 Read Write D15 Notes When RDNn = 0 Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Odd Address ...
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Address bus D15 to D8 Read Write D15 Notes When RDNn = 0 Figure 6.15 Bus Timing for 16-Bit, 2-State Access Space (Word Access) ...
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Access Space: Figures 6.16 to 6.18 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, ...
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Address bus D15 to D8 Read Write D15 Notes When RDNn = 0 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Odd Address ...
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Address bus D15 to D8 Read Write D15 Notes When RDNn = 0 Figure 6.18 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ...
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Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states ( From wait states can be inserted automatically between the T individual area basis ...
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Read Strobe (RD) Timing The read strobe (RD) timing can be changed for individual areas by setting bits RDN3 to RDN0 RDNCR. When the DMAC is used in single address mode, note that if the RD ...
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Extension of Chip Select (CS) Assertion Period Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR ...
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DRAM Interface In this LSI, external space area 2 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM space of 10 Mbytes can be ...
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Data Bus If the ABW2 bit in ACSCR is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, ...
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Basic Timing Figure 6.22 shows the basic access timing for DRAM space. The four states of the basic timing consist of one T output cycle) state, and two T φ Address bus ( ) , ( ) ( ) ...
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Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit DRAMCR. Use the setting that gives the optimum specification values (CAS pulse ...
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Row Address Output State Control If the RAST bit is set DRAMCR, the RAS signal goes low from the beginning of the T state, and the row address hold time and DRAM read access time are ...
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Address bus ( ) , ( ) Read ( ) Data bus ( ) Write ( ) Data bus Figure 6.25 Example of Timing with One Row Address Output Hold State Row address ...
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Precharge State Control When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one T always inserted when DRAM space is accessed. From one to four T setting bits TPC1 and TPC0 in DRACCR. Set ...
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Wait Control When inserting wait states in a DRAM access cycle, program wait insertion is specified. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data ...
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Address bus , ( ) Read ( ) Data bus , ( ) Write ( ) Data bus Figure 6.28 Example of Wait State Insertion Timing (3-State Column Address Output) Rev. 2.00, 03/04, page 130 of 534 T T ...
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Byte Access Control When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.29 shows the control timing for 2-CAS access, and figure 6.30 shows an ...
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This LSI (Address shift size set to 11 bits) RAS (CS2) D15 to D0 Figure 6.30 Example of 2-CAS DRAM Connection 6.6.11 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting ...
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Address bus ( ) , ( ) ( ) Read Data bus ( ) Write ( ) Data bus Figure 6.31 Operation Timing in Fast Page Mode (RAST = 0, CAST = φ Row address Address ...
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RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is ...
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T p φ Address bus Row address ( ) , ( ) ( ) Data bus Figure 6.33 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0) DRAM space read φ ...
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RAS Up Mode To select RAS up mode, clear the RCDM bit DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only ...
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Refresh Control This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when area 2 is ...
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RTCNT RTCOR Refresh request signal and CMF bit setting signal φ setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to three cycles. Use bits RLW1 ...
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Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit ...
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Software standby φ Address bus ( ) , ( ) ( ) Data bus Figure 6.41 Example of Timing when Precharge Time after Self-Refreshing is Extended 6.6.13 DMAC Single Address Transfer Mode and DRAM Interface When burst mode is selected ...
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Address bus ( ) , ( ) ( ) Read Data bus ( ) Write ( ) Data bus Figure 6.42 Example of DACK Output Timing when DDS = 1 (RAST = 0, CAST = 0) When DDS = ...
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Address bus ( ) , ( ) Read ( ) Data bus ( ) Write ( ) Data bus Figure 6.43 Example of DACK Output Timing when DDS = 0 (RAST = 0, CAST = 1) 6.7 Idle Cycle ...
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Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the IDLE1 and IDLE0 bits in BCR are set to either B'01, B'10, or B'11, an idle cycle which is set by the IDLC1 and IDLC0 bits ...
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Bus cycle φ y Address bus (area A) (area B) Data bus Long output floating time (a) No idle cycle insertion (IDLE1 = 0, IDLE0 = 0) Figure 6.45 Example of Idle Cycle Operation ...
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Bus cycle φ y Address bus (area A) (area B) Data bus Long output floating time (a) No idle cycle insertion (IDLE1 = 0, IDLE0 = 0) Figure 6.46 Example of Idle Cycle Operation (Read ...
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Idle Cycle in Case of DRAM Space Access after Normal Space Access DRAM space access following a normal space access, the settings of bits IDLE1, IDLE0, IDLC1, and IDLC0 in BCR are valid. However, in the case of ...
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DRAM space read T p φ Address bus , Data bus Figure 6.49 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads in Different Areas) (IDLE1 = 0, IDLE0 = 1, IDLC1 = 0, IDLC0 = 1, Table ...
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Table 6.7 Idle Cycles in Mixed Accesses to Normal Space and DRAM Space Previous Access Next Access Normal/DRAM Normal/DRAM space space read read (different area) Single address External space transfer access Rev. 2.00, 03/04, page 148 of 534 IDLC1 IDLC0 ...
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Previous Access Next Access Normal/DRAM Normal/DRAM space space read write Normal/DRAM Normal/DRAM space space write read 6.7.2 Pin States in Idle Cycle Table 6.8 shows the pin states in an idle cycle. Table 6.8 Pin States in Idle Cycle Pins ...
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Write Data Buffer Function This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal ...
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Bus Arbitration This LSI has a bus arbiter that arbitrates bus master operations (bus arbitration). There are two bus mastersthe CPU and DMACthat perform read/write operations when they have possession of the bus. Each bus master requests the bus ...
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DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In normal transfer mode or in cycle steal transfer mode, the DMAC releases the bus after a single transfer. In block transfer ...
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Section 7 DMA Controller (DMAC) This LSI has an on-chip DMA controller (DMAC) which can carry out data transfer channels. 7.1 Features • Number of channels: Four channels • Address space: Physical address space (16-Mbyte external ...
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Repeat area set function This function enables data transfer of ring buffer, etc. efficiently because values in the upper bits of the transfer address register are fixed and address values in the specific range are repeated. Repeat area can ...
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Figure 7.1 shows a block diagram of the DMAC. External pins On-chip USB module Internal signals with on-chip USB module Interrupt request signals to CPU for individual channels Legend DMSAR_n: DMA source address register DMDAR_n: DMA destination address register DMTCR_n: ...
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Table 7.1 Pin Configuration Channel Name 0 DMA request 0 DMA transfer acknowledge 0 DACK0 DMA transfer end 0 DREQ0 acceptance acknowledge 1 DMA request 1 DMA transfer acknowledge 1 DACK1 DMA transfer end 1 DREQ1 acceptance acknowledge 2 DMA ...
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Register Descriptions The DMAC has the following registers. • DMA source address register_0 (DMSAR_0) • DMA destination address register_0 (DMDAR_0) • DMA transfer count register_0 (DMTCR_0) • DMA mode control register_0 (DMMDR_0) • DMA address control register_0 (DMACR_0) • ...
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DMA Source Address Register (DMSAR) DMSAR is a 32-bit readable/writable register that specifies the transfer source address. An address update function is provided that updates the register contents to the next transfer source address each time transfer processing is ...
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Normal Transfer Mode: Initial Bit Bit Name Value All Undefined R/W Block Transfer Mode: Initial Bit Bit Name Value 31 to24 All Undefined R ...
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DMA Mode Control Register (DMMDR) DMMDR specifies the operating mode and transfer type. Initial Bit Bit Name Value Rev. 2.00, 03/04, page 160 of 534 R/W Description 1 R/(W)* DMA Active Controls the DMA operation. When ...
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Initial Bit Bit Name Value 14 BEF 0 13 DRAKE 0 12 TENDE 0 11 DREQS 0 10 AMS 0 R/W Description 2 R/(W)* Block Transfer Error Flag Flag that indicates the occurrence of an error during block transfer. If ...
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Initial Bit Bit Name Value 9 MDS1 0 8 MDS0 0 7 DIE 0 Rev. 2.00, 03/04, page 162 of 534 R/W Description R/W Mode Select 1 and 0 R/W These bits specify the activation source, bus mode, and transfer ...
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Initial Bit Bit Name Value 6 IRF 0 5 TCEIE 0 4 SDIR 0 R/W Description 2 R/(W)* Interrupt Request Flag Flag indicating that an interrupt request has occurred and transfer has ended. To clear this bit, the DA bit ...
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Initial Bit Bit Name Value 3 DTSIZE 0 LWSIZE 0 Notes: 1. There is a period when the written value is not reflected immediately. 2. Only 0 can be written after reading 1, ...
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DMA Address Control Register (DMACR) DMACR specifies address register incrementing/decrementing and use of the repeat area function. Initial Bit Bit Name Value 15 SAT1 0 14 SAT0 0 13 SARIE 0 R/W Description R/W Source Address Update Mode R/W ...
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Initial Bit Bit Name Value 12 SARA4 0 11 SARA3 0 10 SARA2 0 9 SARA1 0 8 SARA0 0 Rev. 2.00, 03/04, page 166 of 534 R/W Description Source Address Repeat Area R/W These bits specify the source address ...