DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 482

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

4. Bit rate
• Confirmation, H'06, (one byte): Confirmation of a new bit rate
• Response, H'06, (one byte): Response to confirmation of a new bit rate
The sequence of new bit-rate selection is shown in figure 14.24.
Rev. 2.00, 03/04, page 448 of 534
Confirmation
Response
The calculated operating frequency should be checked to ensure that it is within the range of
minimum to maximum frequencies which are available with the clock modes of the specified
device. When it is out of this range, an operating frequency error is generated.
To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register
(SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral
operating clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that
it is less than 4%. If the error is more than 4%, a bit rate error is generated. The error is
calculated using the following expression:
When the new bit rate is selectable, the rate will be set in the register after sending ACK in
response. The host will send an ACK with the new bit rate for confirmation and the boot
program will response with that rate.
Waiting for one-bit period
Setting a new bit rate
at the specified bit rate
Error (%) = {[
H'06
Host
H'06
(N + 1)
Figure 14.24 New Bit-Rate Selection Sequence
×
φ
B
×
×
H'06 (ACK) with the new bit rate
H'06 (ACK) with the new bit rate
10
64
6
×
Setting a new bit rate
2
(2×n − 1)
H'06 (ACK)
] − 1}
×
100
Setting a new bit rate
Boot program