DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 128

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6.3.6
DRAMCR is used to make DRAM interface settings.
Rev. 2.00, 03/04, page 94 of 534
Bit
15
14
13
12
11 to 9
8
7
DRAM Control Register (DRAMCR)
Bit Name

RAST

CAST

DSET
BE
Initial
Value
0
0
0
0
All 0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit can be read from or written to. However, the
write value should always be 0.
RAS Assertion Timing Select
Selects whether, in DRAM access, the RAS signal is
asserted from the start of the T
or from the falling edge of φ.
Figure 6.4 shows the relationship between the RAST bit
setting and the RAS assertion timing.
0: RAS is asserted from φ falling edge in T
1: RAS is asserted from start of T
Reserved
This bit can be read from or written to. However, the
write value should always be 0.
Column Address Output Cycle Number Select
Selects whether the column address output cycle in
DRAM access comprises 3 states or 2 states.
0: Column address output cycle comprises 2 states
1: Column address output cycle comprises 3 states
Reserved
These bits can be read from or written to. However, the
write value should always be 0.
DRAM Space Setting
Specifies area 2 as DRAM space.
0: Area 2 is specified as normal space
1: Area 2 is specifies as DRAM space
Burst Access Enable
Selects enabling or disabling of burst access to areas
designated as DRAM space. DRAM space burst access
is performed in fast page mode. When using EDO page
mode DRAM, the RD signal must be connected as the
OE signal.
0: Full access
1: Access in fast page mode
r
cycle (rising edge of φ)
r
cycle
r
cycle