DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 446

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Erasing Procedure in User Program Mode: The procedures for download, initialization, and
erasing are shown in figure 14.12.
The procedure program must be executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the
on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 14.4.4, Procedure Program and Storable Area for
Programming Data.
For the downloaded on-chip program area, refer to the RAM map for programming/erasing in
figure 14.10.
A single divided block is erased by one erasing processing. For block divisions, refer to figure
14.4. To erase two or more blocks, update the erase block number and perform the erasing
processing for each block.
Rev. 2.00, 03/04, page 412 of 534
JSR FTDAR setting + 32
Select on-chip program
to be downloaded and
destination by FTDAR
Start erasing procedure
specify download
Set SCO to 1 and
execute download
Set FKEY to H'A5
Set the FPEFEQ
Clear FKEY to 0
Initialization
FPFR = 0 ?
DPFR
parameter
program
1
Yes
Yes
=
0?
Initialization error processing
Download error processing
No
No
1.
Figure 14.12 Erasing Procedure
No
JSR FTDAR setting + 16
Disable interrupts and
bus master operation
Set FEBS parameter
procedure program
Set FKEY to H'5A
Clear FKEY to 0
other than CPU
Required block
End erasing
FPFR = 1 ?
completed?
erasing is
Erasing
1
Yes
Yes
Clear FKEY and erasing
No
error processing
2.
3.
4.
5.
6.