DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 383

IC H8S/2170 MCU FLASH 100-TQFP

DF2170BVTE33V

Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170BVTE33V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.5.4
EP1 has two 64-byte FIFOs in full-speed mode and two 512-byte FIFOs in high-speed mode, but
the user can receive data and read receive data without being aware of this dual-FIFO
configuration. Make sure to confirm that the EP1 FULL bit in IFR0 is set to 1 before reading the
single FIFO.
When one FIFO is full after reception is completed, the EP1 FULL bit in IFR0 is set. After the
first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty,
and so the next packet can be received immediately. When both FIFOs are full, NAK is returned
to the host automatically. When reading of the receive data is completed following data reception,
this operation empties the FIFO that has just been read, and makes it ready to receive the next
packet. If 0-length packet is received from the host, the ACK handshake is returned to the host
regardless of mode (full-speed or high-speed mode) and the EP1 FULL bit in IFR0 is not set.
Note: The dual-configured FIFOs are handled in packet units. Therefore, even if either of FIFOs
is empty because of a short packet, when the packet is received successfully, both FIFOs
become full.
EP1 Bulk-Out Transfer (Dual FIFO)
Rev. 2.00, 03/04, page 349 of 534

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