DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 121

IC H8S/2170 MCU FLASH 100-TQFP

DF2170BVTE33V

Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170BVTE33V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.3.1
ACSCR designates each area in the external address space as either 8-bit access space or 16-bit
access space. ACSCR designates each area in the external address space as either 2-state access
space or 3-state access space.
ACSCR is initialized to H'FF at a reset or in hardware standby mode but not initialized in software
standby mode.
Bit
7
6
5
4
3
2
1
0
Bit Name
ABW3
ABW2
ABW1
ABW0
AST3
AST2
AST1
AST0
Access Control Register (ACSCR)
Initial
Value
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Area 3 to 0 Bus Width Control
These bits select whether the corresponding area is to
be designated as 8-bit access space or 16-bit access
space.
0: Area n is designated as 16-bit access space
1: Area n is designated as 8-bit access space
Area 3 to 0 Access State Control
These bits select whether the corresponding area is to
be designated as 2-state access space or 3-state
access space. Wait state insertion is enabled or
disabled at the same time.
0: Area n is designated as 2-state access space
1: Area n is designated as 3-state access space
Wait state insertion in area n access is disabled
Wait state insertion in area n access is enabled
Rev. 2.00, 03/04, page 87 of 534
(n = 3 to 0)

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