DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 126

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6.3.4
BCR is used for idle cycle settings and enabling or disabling of the write data buffer function.
Rev. 2.00, 03/04, page 92 of 534
Bit
15 to 9
8
7 to 4
3
2
1
0
Bus Control Register (BCR)
Bit Name

WDBE

IDLE1
IDLE0
IDLC1
IDLC0
Initial
Value
All 0
0
All 0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits can be read from or written to. However, the
write value should always be 0.
Write Data Buffer Enable
The write data buffer function can be used for an
external write cycle or DMAC single address transfer
cycle.
0: Write data buffer function not used
1: Write data buffer function used
Reserved
These bits can be read from or written to. However, the
write value should always be 0.
Idle Cycle Enable
These bits enable the idle cycle insertion.
00: Idle cycle insertion is disabled.
01: When read accesses to different areas are
10: When read accesses to different areas are
11: When read accesses to different areas are
Idle Cycle State Number Select
These bits specify the number of idle cycle states to be
inserted.
00: 1 state
01: 2 states
10: 3 states
11: 4 states
continued or external accesses are continued after
a single address transfer, idle cycle insertion is
enabled.
continued, external accesses are continued after a
single address transfer, or write accesses are
continued after a read, idle cycle insertion is
enabled.
continued, external accesses are continued after a
single address transfer, write accesses are
continued after a read, or read accesses are
continued after a write, idle cycle insertion is
enabled.