DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 13

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

5.7
Section 6 Bus Controller (BSC).........................................................................83
6.1
6.2
6.3
6.4
6.5
6.6
5.6.2
5.6.3
5.6.4
Usage Notes ...................................................................................................................... 81
5.7.1
5.7.2
5.7.3
Features............................................................................................................................. 83
Input/Output Pins .............................................................................................................. 85
Register Descriptions ........................................................................................................ 86
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10 Refresh Time Constant Register (RTCOR) ......................................................... 101
Bus Control ....................................................................................................................... 102
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Basic Bus Interface ........................................................................................................... 109
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
DRAM Interface ............................................................................................................... 122
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
Interrupt Control Mode 1 ..................................................................................... 76
Interrupt Exception Handling Sequence .............................................................. 78
Interrupt Response Times .................................................................................... 80
Conflict between Interrupt Generation and Disabling ......................................... 81
Instructions that Disable Interrupts ...................................................................... 82
Interrupts during Execution of EEPMOV Instruction.......................................... 82
Access Control Register (ACSCR) ...................................................................... 87
CS Assertion Period Control Register (CSACR)................................................. 88
Wait Control Register (WTCR) ........................................................................... 90
Bus Control Register (BCR) ................................................................................ 92
Read Strobe Timing Control Register (RDNCR) ................................................ 93
DRAM Control Register (DRAMCR) ................................................................. 94
DRAM Access Control Register (DRACCR)...................................................... 97
Refresh Control Register (REFCR) ..................................................................... 98
Refresh Timer Counter (RTCNT)........................................................................ 101
Area Division....................................................................................................... 102
Address Map ........................................................................................................ 103
Bus Specifications................................................................................................ 105
Memory Interfaces............................................................................................... 107
Chip Select Signals .............................................................................................. 108
Data Size and Data Alignment............................................................................. 109
Valid Strobes ....................................................................................................... 110
Basic Timing........................................................................................................ 110
Wait Control ........................................................................................................ 119
Read Strobe (RD) Timing.................................................................................... 120
Extension of Chip Select (CS) Assertion Period.................................................. 121
Setting DRAM Space........................................................................................... 122
Address Multiplexing .......................................................................................... 122
Data Bus............................................................................................................... 123
Pins Used for DRAM Interface............................................................................ 123
Basic Timing........................................................................................................ 124
Column Address Output Cycle Control ............................................................... 125
Row Address Output State Control...................................................................... 126
Rev. 2.00, 03/04, page xi of xxxii