DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 500
DF2170BVTE33V
Manufacturer Part Number
DF2170BVTE33V
Description
IC H8S/2170 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170BVTE33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170BVTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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When the specified clock signal is input to the EXTAL pin, an internal clock signal output is
ensured after the external clock output stabilization delay time (t
signal output is not ensured during the t
reset state should be retained. Table 15.4 shows the external clock output stabilization delay time
and figure 15.6 shows the timing of the external clock output stabilization delay time.
Table 15.4 External Clock Output Stabilization Delay Time
Conditions: Vcc = 3.0 V to 3.6 V, Vss = 0 V
Note:
15.2
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 2. Therefore, a 16.5-MHz clock should be input to realize the internal 33-MHz operation.
The phase of the rising edge of the internal clock is controlled so as to match that of the rising
edge of the EXTAL pin.
Rev. 2.00, 03/04, page 466 of 534
Item
External clock output
stabilization delay time
V
EXTAL
φ
(internal or external)
Note: * t
CC
*
PLL Circuit
2.7V
DEXT
V
Figure 15.6 Timing of External Clock Output Stabilization Delay Time
t
IH
DEXT
includes the
includes the RES pulse width (t
Symbol
t
DEXT
pulse width (t
*
DEXT
RESW
Min.
500
period, the reset signal should be set to low and the
t
DEXT
).
RESW
*
).
Max.
DEXT
) is passed. Since the clock
Unit
µs
Remark
Figure 15.6
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