DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 142

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Area 3: Area 3 includes the on-chip RAM and internal I/O registers. The space excluding the on-
chip RAM and internal I/O registers is external address space by setting the EXPE bit in MDCR to
1. The on-chip RAM is enabled when the RAME bit is set to 1 in the system control register
(SYSCR); when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding
addresses are in external address space.
When area 3 external address space is accessed, the CS3 signal can be output.
Only the basic bus interface can be used for the area 3 memory interface.
6.4.5
This LSI can output chip select signals (CS3 to CS0) for areas 3 to 0. The signal outputs low when
the corresponding external space area is accessed. Figure 6.8 shows an example of CS3 to CS0
signals output timing.
The CS0 pin is placed in the output state by setting the EXPE bit in MDCR to 1. Pins CS3 to CS1
are placed in the input state after a reset and so the corresponding CS output should be enabled by
setting the PFCR1 register when outputting signals CS3 to CS1.
For details, refer to section 8.11.1, Port Function Control Register 1 (PFCR1).
When area 2 is designated as DRAM space, output CS2 is used as the RAS signal.
Rev. 2.00, 03/04, page 108 of 534
Chip Select Signals
φ
Address bus
Figure 6.8 CSn Signal Output Timing (n = 3 to 0)
T
1
Area n external address
Bus cycle
T
2
T
3