DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 155

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6.5.6
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas. With the CS
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
Figure 6.21 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
Both extension state T
basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non-
insertion can be specified for the T
register, and for the T
Read
(when
RDNn = 0)
Write
Note: n = 3 to 0
Figure 6.21 Example of Timing when Chip Select Assertion Period is Extended
Extension of Chip Select (CS) Assertion Period
φ
Address bus
Data bus
Data bus
t
,
h
state with the lower 4 bits (CSXT3 to CSXT0).
inserted before the basic bus cycle and extension state T
h
state with the upper 4 bits (CSXH3 to CSXH0) in the CSACR
T
h
T
1
Bus cycle
T
Write data
2
Rev. 2.00, 03/04, page 121 of 534
Read data
T
3
t
inserted after the
T
t