ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 111

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.11.4
6.11.5
9111H–AUTO–01/11
Pin Change Interrupt Control Register - PCICR
Pin Change Interrupt Flag Register - PCIFR
• Bit 7..3 - Res: Reserved Bits
• Bit 2 - PCIE2: Pin Change Interrupt Enable 2
• Bit 1 - PCIE1: Pin Change Interrupt Enable 1
• Bit 0 - PCIE0: Pin Change Interrupt Enable 0
• Bit 7..3 - Res: Reserved Bits
• Bit 2 - PCIF2: Pin Change Interrupt Flag 2
Read/Write
Initial Value
Read/Write
Initial Value
These bits are unused bits in the Atmel
zero.
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI2 Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2
Register.
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT14..8 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI1 Interrupt Vector. PCINT14..8 pins are enabled individually by the PCMSK1
Register.
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an
interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from
the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0
Register.
These bits are unused bits in the Atmel ATA6612/ATA6613, and will always read as zero.
When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2
becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bit
Bit
R
7
–
R
0
7
–
0
R
R
6
–
0
6
–
0
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
®
Atmel ATA6612/ATA6613
ATA6612/ATA6613, and will always read as
R
3
–
0
R
3
–
0
PCIE2
PCIF2
R/W
R/W
2
0
2
0
PCIE1
PCIF1
R/W
R/W
1
0
1
0
PCIE0
PCIF0
R/W
R/W
0
0
0
0
PCICR
PCIFR
111