ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 165

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.15.4
6.15.4.1
9111H–AUTO–01/11
Output Compare Unit
Force Output Compare
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a
match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is
executed. Alternatively, the Output Compare Flag can be cleared by software by writing a log-
ical one to its I/O bit location. The Waveform Generator uses the match signal to generate an
output according to operating mode set by the WGM22:0 bits and Compare Output mode
(COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for han-
dling the special cases of the extreme values in some modes of operation (see
Operation” on page
Figure 6-55
Figure 6-55. Output Compare Unit, Block Diagram
The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare
Register to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR2x Register access may seem complex, but this is not case. When the double buffer-
ing is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is
disabled the CPU will access the OCR2x directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced
by writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set
the OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real com-
pare match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set,
cleared or toggled).
shows a block diagram of the Output Compare unit.
168).
bottom
FOCn
top
OCRnx
Waveform Generator
WGMn1:0
= (8-bit Comparator)
DATA BUS
Atmel ATA6612/ATA6613
COMnX1:0
TCNTn
OCFnx (Int.Req.)
OCnx
“Modes of
165