ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 240

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.19.6.3
6.19.6.4
240
Atmel ATA6612/ATA6613
TWI Status Register – TWSR
TWI Data Register – TWDR
Table 6-88.
To calculate bit rates, see
used in the equation.
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the
TWDR contains the last byte received. It is writable while the TWI is not in the process of shift-
ing a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the
Data Register cannot be initialized by the user before the first interrupt occurs. The data in
TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is
simultaneously shifted in. TWDR always contains the last byte present on the bus, except after
a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is
undefined. In the case of a lost bus arbitration, no data is lost in the transition from Master to
Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot
access the ACK bit directly.
TWPS1
0
0
1
1
• Bits 7..3 – TWS: TWI Status
• Bit 2 – Res: Reserved Bit
• Bits 1..0 – TWPS: TWI Prescaler Bits
• Bits 7..0 – TWD: TWI Data Register
Initial Value
Initial Value
Read/Write
Read/Write
These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different sta-
tus codes are described later in this section. Note that the value read from TWSR contains
both the 5-bit status value and the 2-bit prescaler value. The application designer should
mask the prescaler bits to zero when checking the Status bits. This makes status checking
independent of prescaler setting. This approach is used in this datasheet, unless other-
wise noted.
This bit is reserved and will always read as zero.
These bits can be read and written, and control the bit rate prescaler.
These eight bits constitute the next data byte to be transmitted, or the latest data byte
received on the 2-wire Serial Bus.
Bit
Bit
TWI Bit Rate Prescaler
TWD7
TWS7
R/W
R
7
1
7
1
TWD6
TWS6
R/W
TWPS0
0
1
0
1
R
6
1
6
1
“Bit Rate Generator Unit” on page
TWD5
TWS5
R/W
R
5
1
5
1
TWD4
TWS4
R/W
R
4
1
4
1
Prescaler Value
1
4
16
64
TWD3
TWS3
R/W
R
3
1
3
1
TWD2
R/W
R
2
–
0
2
1
237. The value of TWPS1..0 is
TWPS1
TWD1
R/W
R/W
1
0
1
1
TWPS0
TWD0
R/W
R/W
0
0
0
1
9111H–AUTO–01/11
TWSR
TWDR