ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 115

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.12.3
9111H–AUTO–01/11
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
ure 6-28
Figure 6-28. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decre-
mented at each timer clock (clk
source, selected by the Clock Select bits (CS02:0). When no clock source is selected
(CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU,
regardless of whether clk
counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located
in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the
Timer/Counter Control Register B (TCCR0B). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the Output Compare outputs
OC0A and OC0B. For more details about advanced counting sequences and waveform gener-
ation (see
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected
by the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.
count
direction
clear
clk
top
bottom
shows a block diagram of the counter and its surroundings.
Tn
“Modes of Operation” on page
DATA BUS
TCNTn
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
T0
is present or not. A CPU write overrides (has priority over) all
T0
). clk
T0
direction
count
clear
can be generated from an external or internal clock
118).
bottom
Atmel ATA6612/ATA6613
Control Logic
top
TOVn
(Int.Req.)
clk
Tn
T0
in the following.
Clock Select
(From Prescaler)
Detector
Edge
Tn
Fig-
115