ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 195

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.17.2
6.17.2.1
9111H–AUTO–01/11
Clock Generation
Internal Clock Generation – The Baud Rate Generator
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Regis-
ter for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode)
or external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 6-70
Figure 6-70. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
when the UBRRnL Register is written. A clock is generated each time the counter reaches
zero. This clock is the baud rate generator clock output (= f
divides the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate
generator output is used directly by the Receiver’s clock and data recovery units. However,
the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by
the state of the UMSELn, U2Xn and DDR_XCKn bits.
osc
), is loaded with the UBRRn value each time the counter has counted down to zero or
txclk
rxclk
xcki
xcko
fosc
DDR_XCKn
XCKn
Pin
shows a block diagram of the clock generation logic.
xcko
xcki
OSC
Down-Counter
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave
operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
Prescaling
Register
UBRRn
Sync
UBRRn+1
foscn
Detector
UCPOLn
Edge
/2
Atmel ATA6612/ATA6613
Figure
/4
6-70.
osc
/2
/(UBRRn+1)). The Transmitter
DDR_XCKn
U2Xn
0
1
0
1
0
1
1
0
UMSELn
txclk
rxclk
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