ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 38

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4.7
38
Atmel ATA6612/ATA6613
Instruction Execution Timing
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR
Register will not be present.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
the chip. No internal clock division is used.
Figure 6-5
Harvard architecture and the fast-access Register File concept. This is the basic pipelining
concept to obtain up to 1MIPS per MHz with the corresponding unique results for functions per
cost, functions per clocks, and functions per power-unit.
Figure 6-5.
Figure 6-6 on page 39
cycle an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
Read/Write
Bit
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the parallel instruction fetches and instruction executions enabled by the
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
SP15
R/W
R/W
SP7
The Parallel Instruction Fetches and Instruction Executions
15
7
®
architecture is so small that only SPL is needed. In this case, the SPH
clk
shows the internal timing concept for the Register File. In a single clock
SP14
CPU
SP6
R/W
R/W
14
6
SP13
SP5
R/W
R/W
13
5
CPU
T1
, directly generated from the selected clock source for
SP12
R/W
R/W
SP4
12
4
SP11
R/W
R/W
SP3
T2
11
3
SP10
SP2
R/W
R/W
10
2
T3
SP9
SP1
R/W
R/W
9
1
9111H–AUTO–01/11
R/W
R/W
SP8
SP0
8
0
T4
SPH
SPL