ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 99

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9111H–AUTO–01/11
• MOSI/OC2/PCINT3 – Port B, Bit 3
• SS/OC1B/PCINT2 – Port B, Bit 2
• OC1A/PCINT1 – Port B, Bit 1
• ICP1/CLKO/PCINT0 – Port B, Bit 0
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB3.
When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB3.
When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the
PORTB3 bit.
OC2, Output Compare Match Output: The PB3 pin can serve as an external output for the
Timer/Counter2 Compare Match. The PB3 pin has to be configured as an output (DDB3
set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode
timer function.
PCINT3: Pin Change Interrupt source 3. The PB3 pin can serve as an external interrupt
source.
SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an
input regardless of the setting of DDB2. As a Slave, the SPI is activated when this pin is
driven low. When the SPI is enabled as a Master, the data direction of this pin is controlled
by DDB2. When the pin is forced by the SPI to be an input, the pull-up can still be con-
trolled by the PORTB2 bit.
OC1B, Output Compare Match output: The PB2 pin can serve as an external output for
the Timer/Counter1 Compare Match B. The PB2 pin has to be configured as an output
(DDB2 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM
mode timer function.
PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt
source.
OC1A, Output Compare Match output: The PB1 pin can serve as an external output for
the Timer/Counter1 Compare Match A. The PB1 pin has to be configured as an output
(DDB1 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM
mode timer function.
PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt
source.
ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.
CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin.
The divided system clock will be output if the CKOUT Fuse is programmed, regardless of
the PORTB0 and DDB0 settings. It will also be output during reset.
PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt
source.
Table 6-33 on page 100
B to the overriding signals shown in
SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUT-
PUT and SPI SLAVE INPUT.
and
Table 6-34 on page 100
Figure 6-26 on page
Atmel ATA6612/ATA6613
relate the alternate functions of Port
95. SPI MSTR INPUT and SPI
99