ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 220

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.18
6.18.1
6.18.2
220
USART in SPI Mode
Atmel ATA6612/ATA6613
Overview
Clock Generation
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can
be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the
following features:
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Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of oper-
ation the SPI master control logic takes direct control over the USART resources. These
resources include the transmitter and receiver shift register and buffers, and the baud rate
generator. The parity generator and checker, the data and clock recovery logic, and the RX
and TX control logic is disabled. The USART RX and TX control logic is replaced by a com-
mon SPI transfer control logic. However, the pin control logic and interrupt generation logic is
identical in both modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of
the control registers changes when using MSPIM.
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For
USART MSPIM mode of operation only internal clock generation (i.e. master operation) is
supported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set
to one (i.e. as output) for the USART in MSPIM to operate correctly. Preferably the
DDR_XCKn should be set up before the USART in MSPIM is enabled (i.e. TXENn and
RXENn bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous
master mode. The baud rate or UBRRn setting can therefore be calculated using the same
equations (see
Full Duplex, Three-wire Synchronous Data Transfer
Master Operation
Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
LSB First or MSB First Data Transfer (Configurable Data Order)
Queued Operation (Double Buffered)
High Resolution Baud Rate Generator
High Speed Operation (fXCKmax = fCK/2)
Flexible Interrupt Generation
Table 6-83 on page
221).
9111H–AUTO–01/11