ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 234

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.19.4
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Atmel ATA6612/ATA6613
Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been
taken in order to ensure that transmissions will proceed as normal, even if two or more mas-
ters initiate a transmission at the same time. Two problems arise in multi-master systems:
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks
from all masters will be wired-ANDed, yielding a combined clock with a high period equal to
the one from the Master with the shortest high period. The low period of the combined clock is
equal to the low period of the Master with the longest low period. Note that all masters listen to
the SCL line, effectively starting to count their SCL high and low time-out periods when the
combined SCL line goes high or low, respectively.
Figure 6-83. SCL Synchronization Between Multiple Masters
• An algorithm must be implemented allowing only one of the masters to complete the
• Different masters may use different SCL frequencies. A scheme must be devised to
transmission. All other masters should cease transmission when they discover that they
have lost the selection process. This selection process is called arbitration. When a
contending master discovers that it has lost the arbitration process, it should immediately
switch to Slave mode to check whether it is being addressed by the winning master. The
fact that multiple masters have started transmission at the same time should not be
detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted.
synchronize the serial clocks from all masters, in order to let the transmission proceed in a
lockstep fashion. This will facilitate the arbitration process.
SCL from
SCL from
Master A
Master B
SCL Bus
Line
TA
Counting Low Period
low
Masters Start
TB
low
TA
Counting High Period
high
Masters Start
TB
high
9111H–AUTO–01/11