ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 197

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.17.2.3
6.17.2.4
9111H–AUTO–01/11
External Clock
Synchronous Clock Operation
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCKn pin is sampled by a synchronization register to minimize
the chance of meta-stability. The output from the synchronization register must then pass
through an edge detector before it can be used by the Transmitter and Receiver. This process
introduces a two CPU clock period delay and therefore the maximum external XCKn clock fre-
quency is limited by the following equation:
Note that f
to add some margin to avoid possible loss of data due to frequency variations.
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock
input (Slave) or clock output (Master). The dependency between the clock edges and data
sampling or data change is the same. The basic principle is that data input (on RxDn) is sam-
pled at the opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 6-71. Synchronous Mode XCKn Timing
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which
is used for data change. As
changed at rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data
will be changed at falling XCKn edge and sampled at rising XCKn edge.
f
XCK
UCPOL = 1
UCPOL = 0
f
---------- -
OSC
4
osc
depends on the stability of the system clock source. It is therefore recommended
Figure 6-70 on page 195
RxD / TxD
RxD / TxD
XCK
XCK
Figure 6-71
for details.
shows, when UCPOLn is zero the data will be
Atmel ATA6612/ATA6613
Sample
Sample
197