ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 78

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.8.9.1
78
Atmel ATA6612/ATA6613
Watchdog Timer Control Register - WDTCSR
Table 6-24.
• Bit 7 - WDIF: Watchdog Interrupt Flag
• Bit 6 - WDIE: Watchdog Interrupt Enable
• Bit 4 - WDCE: Watchdog Change Enable
• Bit 3 - WDE: Watchdog System Reset Enable
Initial Value
Read/Write
WDTON
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is
configured for interrupt. WDIF is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag.
When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog
Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog
Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the
Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first
time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vec-
tor will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System
Reset Mode). This is useful for keeping the Watchdog Timer security while using the inter-
rupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt.
This should however not be done within the interrupt service routine itself, as this might
compromise the safety-function of the Watchdog System Reset mode. If the interrupt is
not executed before the next time-out, a System Reset will be applied.
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the
WDE bit, and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when
WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple
resets during conditions causing failure, and a safe start-up after the failure.
Bit
0
0
0
0
1
Watchdog Timer Configuration
WDIF
R/W
WDE
7
0
0
0
1
1
x
WDIE
R/W
6
0
WDIE
0
1
0
1
x
WDP3
R/W
5
0
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System Reset
Mode
System Reset Mode
WDCE
R/W
4
0
WDE
R/W
3
X
WDP2
R/W
2
0
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to System
Reset Mode
Reset
WDP1
R/W
1
0
WDP0
R/W
9111H–AUTO–01/11
0
0
WDTCSR