ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 174
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6613P-PLQW
Manufacturer Part Number
ATA6613P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6613P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6613P-PLQW
Manufacturer:
ATMEL
Quantity:
5 000
Part Number:
ATA6613P-PLQW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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6.15.8
6.15.8.1
174
Atmel ATA6612/ATA6613
8-bit Timer/Counter Register Description
Timer/Counter Control Register A – TCCR2A
Table 6-58.
Table 6-59
mode.
Table 6-59.
Note:
• Bits 7:6 – COM2A1:0: Compare Match Output A Mode
Read/Write
Initial Value
COM2A1
COM2A1
These bits control the Output Compare pin (OC2A) behavior. If one or both of the
COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to the OC2A pin must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting.
WGM22:0 bits are set to a normal or CTC mode (non-PWM).
Bit
0
0
1
1
0
0
1
1
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-
shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
pare Match is ignored, but the set or clear is done at TOP. See
169
COM2A1 COM2A0 COM2B1 COM2B0
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
for more details.
R/W
7
0
COM2A0
COM2A0
0
1
0
1
0
1
0
1
R/W
6
0
Table 6-58
Description
Normal port operation, OC0A disconnected.
Toggle OC2A on Compare Match
Clear OC2A on Compare Match
Set OC2A on Compare Match
Description
Normal port operation, OC2A disconnected.
WGM22 = 0: Normal Port Operation, OC0A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
Clear OC2A on Compare Match, set OC2A at TOP
Set OC2A on Compare Match, clear OC2A at TOP
R/W
5
0
shows the COM2A1:0 bit functionality when the
R/W
4
0
R
3
–
0
(1)
R
2
–
0
WGM21 WGM20
“Fast PWM Mode” on page
R/W
1
0
R/W
9111H–AUTO–01/11
0
0
TCCR2A
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