S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 136

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12P Memory Map Control (S12PMMCV1)
3.1.2
The S12PMMC connects the CPU12’s and the S12SBDM’s bus interfaces to the MCU’s on-chip
ressources (memories and peripherals). It arbitrates the bus accesses and detemines all of the MCU’s
memory maps. Furthermore, the S12PMMC is responsible for constraining memory accesses on secured
devices and for selecting the MCU’s functional mode.
3.1.3
The main features of this block are:
3.1.4
The S12PMMC selects the MCU’s functional mode. It also determines the devices behavior in secured and
unsecured state.
3.1.4.1
Two funtional modes are implementes on devices of the S12P product family:
3.1.4.2
S12P devives can be secured to prohibit external access to the on-chip P-Flash. The S12PMMC module
determines the access permissions to the on-chip memories in secured and unsecured state.
3.1.5
Figure 3-1
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Paging capability to support a global 256 KByte memory address space
Bus arbitration between the masters CPU12, S12SBDM to different resources.
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU12, S12SBDM
Generation of system reset when CPU12 accesses an unimplemented address (i.e., an address
which does not belong to any of the on-chip modules) in single-chip modes
Normal Single Chip (NS)
The mode used for running applications.
Special Single Chip Mode (SS)
A debug mode which causes the device to enter BDM Active Mode after each reset. Peripherals
may also provide special debug features in this mode.
shows a block diagram of the S12PMMC.
Overview
Features
Modes of Operation
Block Diagram
Functional Modes
Security
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Freescale Semiconductor