S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 63

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Freescale Semiconductor
Port
Reserved
Register
U
V
-0x0009
Refer to memory map in SoC Guide to determine related module
Write access not applicable for one or more register bits. Refer to register description
Read always returns logic level on pins.
PORTB
0x0000
PORTA
0x0001
0x0002
0x0003
0x0004
DDRA
DDRB
Name
Offset or
Address
0x029C
0x029D
0x029A
0x029B
0x029E
0x029F
0x0290
0x0291
0x0292
0x0293
0x0294
0x0295
0x0296
0x0297
0x0298
0x0299
W
W
W
W
W
R
R
R
R
R
DDRA7
DDRB7
PTU—Port U Data Register
PTIU—Port U input Register
DDRU—Port U Data Direction Register
PIM Reserved
PERU—Port U Pull Device Enable Register
PPSU—Port U Polarity Select Register
SRRU—Port U Slew Rate Register
PIM Reserved
PTV—Port V Data Register
PTIV—Port V Input Register
DDRV—Port V Data Direction Register
PIM Reserved
PERV—Port V Pull Device Enable Register
PPSV—Port V Polarity Select Register
SRRV—Port V Slew Rate Register
PIM Reserved
Bit 7
PB7
PA7
0
= Unimplemented or Reserved
DDRA6
DDRB6
PB6
PA6
6
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-2. Block Memory Map (continued)
DDRA5
DDRB5
Register
PB5
PA5
5
0
DDRA4
DDRB4
PB4
PA4
4
0
DDRA3
DDRB3
PB3
PA3
3
0
Access Reset Value
DDRA2
DDRB2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PB2
R
R
R
R
R
R
PA2
Port Integration Module (S12HYPIMV1)
2
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DDRA1
DDRB1
3
3
PB1
PA1
1
0
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DDRA0
DDRB0
Bit 0
PB0
PA0
0
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