S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 464

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (S12SPIV5)
13.3.2.2
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
464
Module Base +0x0001
Reset
LSBFE
SSOE
Field
1
0
W
R
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE as shown in
progress and force the SPI system into idle state.
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
SPI Control Register 2 (SPICR2)
0
0
7
MODFEN
= Unimplemented or Reserved
0
0
1
1
XFRW
0
6
Table 13-2. SPICR1 Field Descriptions (continued)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
SSOE
Figure 13-4. SPI Control Register 2 (SPICR2)
0
1
0
1
Table 13-3. SS Input / Output Selection
0
0
5
Table
SS input with MODF feature
13-3. In master mode, a change of this bit will abort a transmission in
SS is slave select output
MODFEN
SS not used by SPI
SS not used by SPI
Master Mode
0
4
Description
BIDIROE
0
3
0
0
2
Slave Mode
SS input
SS input
SS input
SS input
SPISWAI
Freescale Semiconductor
0
1
SPC0
0
0