S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 137

MCU 64K FLASH AUTO 64-LQFP

S9S12HY64J0MLH

Manufacturer Part Number
S9S12HY64J0MLH
Description
MCU 64K FLASH AUTO 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S9S12HY64J0MLH

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-LQFP
Controller Family/series
S12
No. Of I/o's
50
Ram Memory Size
4KB
Cpu Speed
64MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
S12HY
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
DEMO9S12HY64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S12HY64J0MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
3.2
The S12PMMC uses two external pins to determine the devices operating mode: RESET and MODC
(Figure
3.3
3.3.1
A summary of the registers associated with the S12PMMC block is shown in
descriptions of the registers and bits are given in the subsections that follow.
Freescale Semiconductor
(See DUG)
(See DUG)
Pin Name
RESET
MODC
3-3) See Device User Guide (DUG) for the mapping of these signals to device pins.
External Signal Description
Memory Map and Registers
Module Memory Map
MMC
Pin Functions
D-Flash
Table 3-3. External System Pins Associated With S12PMMC
RESET
MODC
BDM
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Address Decoder & Priority
Figure 3-1. S12PMMC Block Diagram
Target Bus Controller
The RESET pin is used the select the MCU’s operating mode.
The MODC pin is captured at the rising edge of the RESET pin. The captured
value determines the MCU’s operating mode.
P-Flash
RAM
Description
CPU
Peripherals
S12P Memory Map Control (S12PMMCV1)
Figure
DBG
3-2. Detailed
137

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