S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 275

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5
7.5.1
All reset sources are listed in
priorities.
7.5.2
Upon detection of any reset of
cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU waits
for additional 256 PLLCLK cycles and then samples the RESET pin to determine the originating source.
Table 7-26
Freescale Semiconductor
Resets
shows which vector will be fetched.
Sampled RESET Pin
General
Description of Reset Operation
(256 cycles after
While System Reset is asserted the PLLCLK runs with the frequency
f
VCORST
release)
1
1
1
0
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
External pin RESET
Clock Monitor Reset
.
Reset Source
COP Reset
Table
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table
Oscillator monitor
fail pending
7-25. Refer to MCU specification for related vector addresses and
Table 7-26. Reset Vector Selection
7-25, an internal circuit drives the RESET pin low for 512 PLLCLK
Table 7-25. Reset Summary
X
0
1
0
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
NOTE
time out
pending
COP
X
X
0
1
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
Local Enable
None
None
None
None
Illegal Address Reset
Illegal Address Reset
External pin RESET
Clock Monitor Reset
External pin RESET
Vector Fetch
COP Reset
POR
POR
LVR
LVR
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