S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 200

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12S Debug Module (S12SDBGV2)
Table 6-23
corresponding TAG bit is set since the match occurs based on the tagged opcode reaching the execution
stage of the instruction queue.
200
(Comparator A)
COMPE
Field
RWE
NDB
BRK
TAG
RW
5
4
3
2
1
0
shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the
Tag Select— This bit controls whether the comparator match has immediate effect, causing an immediate
state sequencer transition or tag the opcode at the matched address. Tagged opcodes trigger only if they
reach the execution stage of the instruction queue.
0 Allow state sequencer transition immediately on match
1 On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition
Break— This bit controls whether a comparator match terminates a debug session immediately, independent
of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled
using the DBGC1 bit DBGBRK.
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same
register is set.
0 Write cycle is matched1Read cycle is matched
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
associated comparator.This bit is ignored if the TAG bit in the same register is set
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
register value or when the data bus differs from the register value. This bit is ignored if the TAG bit in the same
register is set. This bit is only available for comparator A.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled
RWE Bit
tracing, if active, is terminated and the module disarmed.
0
0
1
1
1
1
Table 6-22. DBGXCTL Field Descriptions (continued)
Table 6-23. Read or Write Comparison Logic Table
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
RW Bit
x
x
0
0
1
1
RW Signal
0
1
0
1
0
1
Description
RW not used in comparison
RW not used in comparison
Write data bus
Read data bus
Comment
No match
No match
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