S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 47

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.11
Consult the S12 CPU manual and the S12SINT section for information on exception processing.
1.11.1
Table 1-11. lists all Reset sources and the vector locations. Resets are explained in detail in the Section
Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
1.11.2
Table 1-12
Chapter 4, “Interrupt Module
the vectors.
Freescale Semiconductor
Vector base + 0xEC
Vector base + 0xF8
Vector base + 0xE4
Vector base+ 0xEE
Vector base+ 0xEA
Vector base+ 0xE8
Vector base+ 0xE6
Vector base+ 0xE2
Vector Address
Vector base+ 0xF6
Vector base+ 0xF4
Vector base+ 0xF2
Vector base+ 0xF0
Vector Address
Resets and Interrupts
lists all interrupt sources and vectors in the default order of priority. The interrupt module (see
Resets
Vectors
0xFFFC
0xFFFE
0xFFFE
0xFFFE
0xFFFE
0xFFFA
(1)
Table 1-12. Interrupt Vector Locations (Sheet 1 of 3)
Table 1-11. Reset Sources and Vector Locations
(S12SINTV1)) provides an interrupt vector base register (IVBR) to relocate
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Unimplemented instruction trap
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
TIM0 timer channel 0
TIM0 timer channel 1
TIM0 timer channel 2
TIM0 timer channel 3
TIM0 timer channel 4
TIM0 timer channel 5
TIM0 timer channel 6
COP watchdog reset
External pin RESET
Clock monitor reset
Real time interrupt
Interrupt Source
Reset Source
XIRQ
SWI
IRQ
Mask
Mask
None
None
None
None
None
None
None
None
CCR
CCR
X Bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
Device Overview MC9S12HY/HA-Family
IRQCR (XIRQEN)
CPMUINT (RTIE)
IRQCR (IRQEN)
TIM0TIE (C0I)
TIM0TIE (C1I)
TIM0TIE (C2I)
TIM0TIE (C3I)
TIM0TIE (C4I)
TIM0TIE (C5I)
TIM0TIE (C6I)
Local Enable
Local Enable
None
None
None
None
None
None
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