S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 251

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.2.14
The CPMULVCTL register allows the configuration of the low-voltage detect features.
Read: Anytime
Write: LVIE and LVIF are write anytime, LVDS is read only
Freescale Semiconductor
0x02F1
The Reset state of LVDS and LVIF depends on the external supplied VDDA level
Reset
LVDS
Field
LVIE
LVIF
2
1
0
W
R
Low-Voltage Detect Status Bit — This read-only status bit reflects the voltage level on VDDA. Writes have no
effect.
0 Input voltage V
1 Input voltage V
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
Low Voltage Control Register (CPMULVCTL)
0
0
7
= Unimplemented or Reserved
Figure 7-17. Low Voltage Control Register (CPMULVCTL)
0
0
6
DDA
DDA
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 7-14. CPMULVCTL Field Descriptions
is above level V
is below level V
0
0
5
LVIA
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
LVID
and FPM.
or RPM.
0
0
4
Description
0
0
3
LVDS
U
2
LVIE
0
1
LVIF
U
0
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