S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 183

MCU 64K FLASH AUTO 64-LQFP

S9S12HY64J0MLH

Manufacturer Part Number
S9S12HY64J0MLH
Description
MCU 64K FLASH AUTO 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S9S12HY64J0MLH

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LCD, Motor control PWM, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-LQFP
Controller Family/series
S12
No. Of I/o's
50
Ram Memory Size
4KB
Cpu Speed
64MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
S12HY
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
DEMO9S12HY64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S12HY64J0MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 6
S12S Debug Module (S12SDBGV2)
6.1
The S12SDBG module provides an on-chip trace buffer with flexible triggering capability to allow
non-intrusive debug of application software. The S12SDBG module is optimized for S12SCPU
debugging.
Typically the S12SDBG module is used in conjunction with the S12SBDM module, whereby the user
configures the S12SDBG module for a debugging session over the BDM interface. Once configured the
S12SDBG module is armed and the device leaves BDM returning control to the user program, which is
then monitored by the S12SDBG module. Alternatively the S12SDBG module can be configured over a
serial interface using SWI routines.
6.1.1
COF: Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt.
BDM: Background Debug Mode
S12SBDM: Background Debug Module
DUG: Device User Guide, describing the features of the device into which the DBG is integrated.
WORD: 16 bit data entity
Data Line: 20 bit data entity
CPU: S12SCPU module
DBG: S12SDBG module
POR: Power On Reset
Revision Number
02.07
02.08
02.09
Introduction
Glossary Of Terms
13.DEC.2007
09.MAY.2008
29.MAY.2008
Revision
Date
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Sections
Affected
General
6.4.5.4
6.5
Table 6-1. Revision History
Freescale Semiconductor
Added application information
Spelling corrections. Revision history format changed.
Added note for end aligned, PurePC, rollover case.
Summary of Changes

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