D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 179

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

BSCS201A_000020020100
This LSI has an on-chip bus controller (BSC) that manages the external space divided into eight
areas.
The bus controller also has a bus arbitration function, and controls the operation of the bus
masters—the CPU, DMA controller (DMAC) and data transfer controller (DTC).
6.1
• Manages external space in area units
• Basic bus interface
• Burst ROM interface
• DRAM interface
• Bus arbitration function
Manages the external space divided into eight areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM, or DRAM, interface can be set
Chip select signals (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
Burst ROM interface can be set independently for areas 0 and 1
DRAM interface can be set for areas 2 to 5
Includes a bus arbiter that arbitrates bus right between the CPU, DMAC, and DTC
Features
Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 119 of 980
Section 6 Bus Controller (BSC)
REJ09B0050-0600