D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 766

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 19 Flash Memory (0.35-μm F-ZTAT Version)
19.7
A software method, using the CPU, is employed to program and erase flash memory in the on-
board programming modes. Depending on the FLMCR1 and FLMCR2 setting, the flash memory
operates in one of the following four modes: program mode, erase mode, program-verify mode,
and erase-verify mode. The programming control program in boot mode and the user
program/erase program in user mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 19.7.1, Program/Program-Verify and section 19.7.2,
Erase/Erase-Verify, respectively.
19.7.1
When programming data or programs to the flash memory, the program/program-verify flowchart
shown in figure 19.7 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be programmed to the flash memory without subjecting
the chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128-
4. Consecutively transfer 128 bytes of data in byte units from the programming data area,
5. The time during which the P bit is set to 1 is the programming time. Figure 19.7 shows the
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits
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programming has already been performed.
performed even if programming fewer than 128 bytes. In this case, H'FF data must be written
to the extra addresses.
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation and additional programming data computation according to
figure 19.7.
reprogramming data area, or additional-programming data area to the flash memory. The
program address and 128-byte data are latched in the flash memory. The lower 8 bits of the
start address in the flash memory destination area must be H'00 or H'80.
allowable programming times.
Set a value greater than (y + z2 + α + β) µs as the WDT overflow period.
are B'00. Verify data can be read in words from the address to which a dummy write was
performed.
Flash Memory Programming/Erasing
Program/Program-Verify