D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 35

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

14.7 Operation in Smart Card Interface Mode .......................................................................... 604
14.8 IrDA Operation ................................................................................................................. 616
14.9 SCI Interrupts.................................................................................................................... 619
14.10 Usage Notes ...................................................................................................................... 622
Section 15 I
15.1 Features ............................................................................................................................. 629
15.2 Input/Output Pins .............................................................................................................. 631
15.3 Register Descriptions ........................................................................................................ 632
15.4 Operation........................................................................................................................... 643
14.6.5 Simultaneous Serial Data Transmission and Reception
14.7.1 Pin Connection Example...................................................................................... 604
14.7.2 Data Format (Except for Block Transfer Mode) .................................................. 605
14.7.3 Block Transfer Mode ........................................................................................... 606
14.7.4 Receive Data Sampling Timing and Reception Margin....................................... 606
14.7.5 Initialization ......................................................................................................... 608
14.7.6 Data Transmission (Except for Block Transfer Mode) ........................................ 608
14.7.7 Serial Data Reception (Except for Block Transfer Mode) ................................... 612
14.7.8 Clock Output Control........................................................................................... 613
14.9.1 Interrupts in Normal Serial Communication Interface Mode............................... 619
14.9.2 Interrupts in Smart Card Interface Mode ............................................................. 621
14.10.1 Module Stop Mode Setting .................................................................................. 622
14.10.2 Break Detection and Processing........................................................................... 622
14.10.3 Mark State and Break Sending............................................................................. 622
14.10.4 Receive Error Flags and Transmit Operations
14.10.5 Relation between Writes to TDR and the TDRE Flag ......................................... 623
14.10.6 Restrictions on Use of DMAC or DTC................................................................ 623
14.10.7 Operation in Case of Mode Transition................................................................. 624
15.3.1 I
15.3.2 I
15.3.3 I
15.3.4 I
15.3.5 I
15.3.6 Slave Address Register (SAR) ............................................................................. 641
15.3.7 I
15.3.8 I
15.3.9 I
15.4.1 I
(Clocked Synchronous Mode) ............................................................................. 602
(Clocked Synchronous Mode Only)..................................................................... 623
2
2
2
2
2
2
2
2
2
2
C Bus Control Register A (ICCRA) .................................................................. 633
C Bus Control Register B (ICCRB)................................................................... 635
C Bus Mode Register (ICMR) ........................................................................... 636
C Bus Interrupt Enable Register (ICIER) .......................................................... 637
C Bus Status Register (ICSR)............................................................................ 639
C Bus Transmit Data Register (ICDRT)............................................................ 642
C Bus Receive Data Register (ICDRR) ............................................................. 642
C Bus Shift Register (ICDRS) ........................................................................... 642
C Bus Format..................................................................................................... 643
C Bus Interface2 (IIC2) (Option)
............................................................ 629
Rev.6.00 Mar. 18, 2009 Page xxxiii of lviii
REJ09B0050-0600