D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 26

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

6.4
6.5
6.6
6.7
6.8
6.9
6.10 Bus Release....................................................................................................................... 206
6.11 Bus Arbitration.................................................................................................................. 209
Rev.6.00 Mar. 18, 2009 Page xxiv of lviii
REJ09B0050-0600
6.3.12 Refresh Time Constant Register (RTCOR) ......................................................... 144
Operation .......................................................................................................................... 144
6.4.1
6.4.2
6.4.3
6.4.4
Basic Bus Interface ........................................................................................................... 150
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
DRAM Interface ............................................................................................................... 165
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
6.6.8
6.6.9
6.6.10 Byte Access Control ............................................................................................ 176
6.6.11 Burst Operation.................................................................................................... 177
6.6.12 Refresh Control.................................................................................................... 182
6.6.13 DMAC Single Address Transfer Mode and DRAM Interface............................. 187
Burst ROM Interface......................................................................................................... 190
6.7.1
6.7.2
6.7.3
Idle Cycle.......................................................................................................................... 193
6.8.1
6.8.2
Write Data Buffer Function .............................................................................................. 204
6.10.1 Operation ............................................................................................................. 206
6.10.2 Pin States in External Bus Released State............................................................ 207
6.10.3 Transition Timing ................................................................................................ 208
Area Division....................................................................................................... 144
Bus Specifications................................................................................................ 146
Memory Interfaces ............................................................................................... 148
Chip Select Signals .............................................................................................. 149
Data Size and Data Alignment............................................................................. 150
Valid Strobes........................................................................................................ 152
Basic Timing........................................................................................................ 153
Wait Control ........................................................................................................ 161
Read Strobe (RD) Timing.................................................................................... 162
Extension of Chip Select (CS) Assertion Period.................................................. 163
Setting DRAM Space........................................................................................... 165
Address Multiplexing........................................................................................... 165
Data Bus............................................................................................................... 166
Pins Used for DRAM Interface............................................................................ 167
Basic Timing........................................................................................................ 168
Column Address Output Cycle Control ............................................................... 169
Row Address Output State Control...................................................................... 170
Precharge State Control ....................................................................................... 172
Wait Control ........................................................................................................ 173
Basic Timing........................................................................................................ 190
Wait Control ........................................................................................................ 192
Write Access ........................................................................................................ 192
Operation ............................................................................................................. 193
Pin States in Idle Cycle ........................................................................................ 204